mirror of
https://github.com/espressif/esp-idf.git
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282 lines
13 KiB
C
282 lines
13 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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************************* ESP32 Root Clock Source ****************************
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* 1) Internal 8MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description)
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*
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* This RC oscillator generates a ~8.5MHz clock signal output as the RC_FAST_CLK.
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* The ~8.5MHz signal output is also passed into a configurable divider, which by default divides the input clock
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* frequency by 256, to generate a RC_FAST_D256_CLK (usually referred as 8md256 or simply d256 in reg. description).
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*
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* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
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*
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* 2) External 2~40MHz Crystal Clock: XTAL
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*
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* 3) Internal 150kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
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*
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* This RC oscillator generates a ~150kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
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* can be computed in runtime through calibration.
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*
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* 4) External 32kHz Crystal Clock (optional): XTAL32K
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*
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* The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the 32K_XP and 32K_XN pins
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* or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the 32K_XN pin.
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* Additionally, a 1nF capacitor must be placed between the 32K_XP pin and ground. In this case, the 32K_XP pin
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* cannot be used as a GPIO pin.
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*
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* XTAL32K_CLK can also be calibrated to get its exact frequency.
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*/
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/* With the default value of CK8M_DFREQ = 172, RC_FAST clock frequency is 8.5 MHz +/- 7% */
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#define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
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/* With the default value of DCAP, range is +/- 5% */
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#define SOC_CLK_RC_SLOW_FREQ_APPROX 150000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
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#define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /*!< Approximate RC_FAST_D256_CLK frequency in Hz */
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#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
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// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
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// {loc}: EXT, INT
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// {type}: XTAL, RC
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// [attr] - optional: [frequency], FAST, SLOW
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/**
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* @brief Root clock
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*/
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typedef enum {
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SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 8MHz RC oscillator */
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SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 150kHz RC oscillator */
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SOC_ROOT_CLK_EXT_XTAL, /*!< External 2~40MHz crystal */
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SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */
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} soc_root_clk_t;
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/**
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* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */
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SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_APLL = 3, /*!< Select APLL_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
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} soc_cpu_clk_src_t;
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/**
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* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
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} soc_rtc_slow_clk_src_t;
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/**
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* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_RTC_FAST_CLK_SRC_XTAL_D4 = 0, /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
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} soc_rtc_fast_clk_src_t;
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// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
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// {[upstream]clock_name}: APB, APLL, (BB)PLL, etc.
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// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
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/**
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* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
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*
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* @note enum starts from 1, to save 0 for special purpose
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*/
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typedef enum {
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// For CPU domain
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SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or APLL by configuring soc_cpu_clk_src_t */
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// For RTC domain
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SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D4 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
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SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
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// For digital domain: peripherals, WIFI, BLE
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SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */
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SOC_MOD_CLK_PLL_D2, /*!< PLL_D2_CLK is derived from PLL, it has a fixed divider of 2 */
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SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
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SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */
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SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK comes from the internal 8MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */
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SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external crystal (2~40MHz) */
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SOC_MOD_CLK_REF_TICK, /*!< REF_TICK is derived from APB, it has a fixed frequency of 1MHz even when APB frequency changes */
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SOC_MOD_CLK_APLL, /*!< APLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */
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} soc_module_clk_t;
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//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of GPTimer
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*
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* The following code can be used to iterate all possible clocks:
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* @code{c}
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* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
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* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
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* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
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* // Test GPTimer with the clock `clk`
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* }
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* @endcode
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*/
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#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB}
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/**
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* @brief Type of GPTimer clock source
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*/
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typedef enum {
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GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
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GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
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} soc_periph_gptimer_clk_src_t;
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/**
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* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
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*/
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typedef enum {
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TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group source clock is APB */
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TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */
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} soc_periph_tg_clk_src_legacy_t;
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//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of LCD
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*/
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#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_APLL, SOC_MOD_CLK_XTAL}
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/**
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* @brief Type of LCD clock source
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*/
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typedef enum {
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LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (default to 160MHz) as the source clock */
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LCD_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
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LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (default to 160MHz) as the default choice */
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} soc_periph_lcd_clk_src_t;
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//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of RMT
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*/
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#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_REF_TICK}
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/**
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* @brief Type of RMT clock source
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*/
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typedef enum {
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RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
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RMT_CLK_SRC_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< Select REF_TICK as the source clock */
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RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
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} soc_periph_rmt_clk_src_t;
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/**
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* @brief Type of RMT clock source, reserved for the legacy RMT driver
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*/
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typedef enum {
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RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB CLK */
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RMT_BASECLK_REF = SOC_MOD_CLK_REF_TICK, /*!< RMT source clock is REF_TICK */
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RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
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} soc_periph_rmt_clk_src_legacy_t;
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///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
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/**
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* @brief Type of UART clock source, reserved for the legacy UART driver
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*/
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typedef enum {
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UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */
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UART_SCLK_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< UART source clock is REF_TICK */
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UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
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} soc_periph_uart_clk_src_legacy_t;
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//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of MCPWM Timer
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*/
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#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_D2}
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/**
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* @brief Type of MCPWM timer clock source
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*/
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typedef enum {
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MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (160MHz) as the source clock */
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MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the default clock choice */
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} soc_periph_mcpwm_timer_clk_src_t;
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/**
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* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
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*/
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#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_APB}
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/**
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* @brief Type of MCPWM capture clock source
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*/
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typedef enum {
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MCPWM_CAPTURE_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
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MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< SElect APB as the default clock choice */
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} soc_periph_mcpwm_capture_clk_src_t;
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///////////////////////////////////////////////////I2S//////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of I2S
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*/
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#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_APLL}
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/**
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* @brief I2S clock source enum
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*
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*/
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typedef enum {
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the default source clock */
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I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the source clock */
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I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
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} soc_periph_i2s_clk_src_t;
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/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of I2C
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*/
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#define SOC_I2C_CLKS {SOC_MOD_CLK_APB}
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/**
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* @brief Type of I2C clock source.
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*/
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typedef enum {
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I2C_CLK_SRC_APB = SOC_MOD_CLK_APB,
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I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB,
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} soc_periph_i2c_clk_src_t;
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//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of SDM
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*/
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#define SOC_SDM_CLKS {SOC_MOD_CLK_APB}
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/**
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* @brief Sigma Delta Modulator clock source
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*/
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typedef enum {
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SDM_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
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SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
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} soc_periph_sdm_clk_src_t;
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#ifdef __cplusplus
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}
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#endif
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