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75 lines
3.3 KiB
C
75 lines
3.3 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __HWCRYPTO_REG_H__
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#define __HWCRYPTO_REG_H__
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#include "soc.h"
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/* registers for RSA acceleration via Multiple Precision Integer ops */
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#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000)
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/* RB & Z use the same memory block, depending on phase of operation */
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#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
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#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
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#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400)
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#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600)
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#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800)
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#define RSA_MODEXP_MODE_REG (DR_REG_RSA_BASE + 0x804)
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#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x808)
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#define RSA_MULT_MODE_REG (DR_REG_RSA_BASE + 0x80c)
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#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x810)
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#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x814)
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#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x814) /* same */
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#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x818)
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/* Backwards compatibility register names used pre-ESP32S2 */
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#define RSA_CLEAN_REG (RSA_QUERY_CLEAN_REG)
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#define RSA_INTERRUPT_REG (RSA_CLEAR_INTERRUPT_REG)
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#define RSA_START_MODEXP_REG (RSA_MODEXP_START_REG)
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/* SHA acceleration registers */
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#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x00)
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#define SHA_1_START_REG ((DR_REG_SHA_BASE) + 0x80)
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#define SHA_1_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x84)
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#define SHA_1_LOAD_REG ((DR_REG_SHA_BASE) + 0x88)
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#define SHA_1_BUSY_REG ((DR_REG_SHA_BASE) + 0x8c)
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#define SHA_256_START_REG ((DR_REG_SHA_BASE) + 0x90)
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#define SHA_256_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x94)
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#define SHA_256_LOAD_REG ((DR_REG_SHA_BASE) + 0x98)
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#define SHA_256_BUSY_REG ((DR_REG_SHA_BASE) + 0x9c)
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#define SHA_384_START_REG ((DR_REG_SHA_BASE) + 0xa0)
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#define SHA_384_CONTINUE_REG ((DR_REG_SHA_BASE) + 0xa4)
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#define SHA_384_LOAD_REG ((DR_REG_SHA_BASE) + 0xa8)
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#define SHA_384_BUSY_REG ((DR_REG_SHA_BASE) + 0xac)
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#define SHA_512_START_REG ((DR_REG_SHA_BASE) + 0xb0)
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#define SHA_512_CONTINUE_REG ((DR_REG_SHA_BASE) + 0xb4)
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#define SHA_512_LOAD_REG ((DR_REG_SHA_BASE) + 0xb8)
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#define SHA_512_BUSY_REG ((DR_REG_SHA_BASE) + 0xbc)
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/* AES acceleration registers */
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#define AES_START_REG ((DR_REG_AES_BASE) + 0x00)
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#define AES_IDLE_REG ((DR_REG_AES_BASE) + 0x04)
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#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x08)
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#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x10)
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#define AES_TEXT_BASE ((DR_REG_AES_BASE) + 0x30)
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#define AES_ENDIAN ((DR_REG_AES_BASE) + 0x40)
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#endif
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