esp-idf/components/ulp/ld/lp_core_riscv.ld

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "soc/soc.h"
ENTRY(reset_vector)
MEMORY
{
/*first 128byte for exception/interrupt vectors*/
vector_table(RX) : ORIGIN = SOC_RTC_DRAM_LOW, LENGTH = 0x80
ram(RWX) : ORIGIN = SOC_RTC_DRAM_LOW + 0x80, LENGTH = CONFIG_ULP_COPROC_RESERVE_MEM - 0x80 - CONFIG_ULP_SHARED_MEM
}
SECTIONS
{
.vector.text :
{
/*exception/interrupt vectors*/
__mtvec_base = .;
KEEP (*(.init.vector .init.vector.*))
} > vector_table
. = ORIGIN(ram);
.text ALIGN(4):
{
*(.text.vectors) /* Default reset vector must link to offset 0x80 */
*(.text)
*(.text*)
} >ram
.rodata ALIGN(4):
{
*(.rodata)
*(.rodata*)
} > ram
.data ALIGN(4):
{
*(.data)
*(.data*)
*(.sdata)
*(.sdata*)
} > ram
.bss ALIGN(4) :
{
*(.bss)
*(.bss*)
*(.sbss)
*(.sbss*)
PROVIDE(end = .);
} >ram
__stack_top = ORIGIN(ram) + LENGTH(ram);
}