mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
93c784e1c8
Alarm will be disabled by hardware when alarm event happend. In the ISR, if auto-reload is enabled, we should re-enable the alarm. If the alarm target value is changed in user's callback, the alarm will be reenabled as well. Closes https://github.com/espressif/esp-idf/issues/7001 Closes https://github.com/espressif/esp-idf/issues/8095
519 lines
23 KiB
C
519 lines
23 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "esp_log.h"
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_api.h"
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#include "driver/timer.h"
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#include "driver/periph_ctrl.h"
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#include "hal/timer_hal.h"
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#include "soc/rtc.h"
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static const char *TIMER_TAG = "timer_group";
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#define TIMER_CHECK(a, str, ret_val) \
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if (!(a)) { \
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ESP_LOGE(TIMER_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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}
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#define TIMER_GROUP_NUM_ERROR "TIMER GROUP NUM ERROR"
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#define TIMER_NUM_ERROR "HW TIMER NUM ERROR"
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#define TIMER_PARAM_ADDR_ERROR "HW TIMER PARAM ADDR ERROR"
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#define TIMER_NEVER_INIT_ERROR "HW TIMER NEVER INIT ERROR"
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#define TIMER_COUNT_DIR_ERROR "HW TIMER COUNTER DIR ERROR"
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#define TIMER_AUTORELOAD_ERROR "HW TIMER AUTORELOAD ERROR"
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#define TIMER_SCALE_ERROR "HW TIMER SCALE ERROR"
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#define TIMER_ALARM_ERROR "HW TIMER ALARM ERROR"
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#define DIVIDER_RANGE_ERROR "HW TIMER divider outside of [2, 65536] range error"
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#define TIMER_ENTER_CRITICAL(mux) portENTER_CRITICAL_SAFE(mux);
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#define TIMER_EXIT_CRITICAL(mux) portEXIT_CRITICAL_SAFE(mux);
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typedef struct {
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timer_isr_t fn; /*!< isr function */
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void *args; /*!< isr function args */
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timer_isr_handle_t timer_isr_handle; /*!< interrupt handle */
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timer_group_t isr_timer_group; /*!< timer group of interrupt triggered */
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} timer_isr_func_t;
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typedef struct {
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timer_hal_context_t hal;
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timer_isr_func_t timer_isr_fun;
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} timer_obj_t;
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static timer_obj_t *p_timer_obj[TIMER_GROUP_MAX][TIMER_MAX] = {0};
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static portMUX_TYPE timer_spinlock[TIMER_GROUP_MAX] = {portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED};
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esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t *timer_val)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_val != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_get_counter_value(&(p_timer_obj[group_num][timer_num]->hal), timer_val);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_num, double *time)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(time != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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uint64_t timer_val;
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esp_err_t err = timer_get_counter_value(group_num, timer_num, &timer_val);
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if (err == ESP_OK) {
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uint32_t div;
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timer_hal_get_divider(&(p_timer_obj[group_num][timer_num]->hal), &div);
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*time = (double)timer_val * div / rtc_clk_apb_freq_get();
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#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
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if (timer_hal_get_use_xtal(&(p_timer_obj[group_num][timer_num]->hal))) {
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*time = (double)timer_val * div / ((int)rtc_clk_xtal_freq_get() * 1000000);
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}
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#endif
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}
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return err;
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}
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esp_err_t timer_set_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t load_val)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_set_counter_value(&(p_timer_obj[group_num][timer_num]->hal), load_val);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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esp_err_t timer_start(timer_group_t group_num, timer_idx_t timer_num)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), TIMER_START);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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esp_err_t timer_pause(timer_group_t group_num, timer_idx_t timer_num)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), TIMER_PAUSE);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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esp_err_t timer_set_counter_mode(timer_group_t group_num, timer_idx_t timer_num, timer_count_dir_t counter_dir)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(counter_dir < TIMER_COUNT_MAX, TIMER_COUNT_DIR_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_set_counter_increase(&(p_timer_obj[group_num][timer_num]->hal), counter_dir);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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esp_err_t timer_set_auto_reload(timer_group_t group_num, timer_idx_t timer_num, timer_autoreload_t reload)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(reload < TIMER_AUTORELOAD_MAX, TIMER_AUTORELOAD_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_set_auto_reload(&(p_timer_obj[group_num][timer_num]->hal), reload);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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esp_err_t timer_set_divider(timer_group_t group_num, timer_idx_t timer_num, uint32_t divider)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(divider > 1 && divider < 65537, DIVIDER_RANGE_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_set_divider(&(p_timer_obj[group_num][timer_num]->hal), (uint16_t) divider);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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esp_err_t timer_set_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_value)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_set_alarm_value(&(p_timer_obj[group_num][timer_num]->hal), alarm_value);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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esp_err_t timer_get_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t *alarm_value)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(alarm_value != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_get_alarm_value(&(p_timer_obj[group_num][timer_num]->hal), alarm_value);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_alarm_t alarm_en)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(alarm_en < TIMER_ALARM_MAX, TIMER_ALARM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_set_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal), alarm_en);
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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static void IRAM_ATTR timer_isr_default(void *arg)
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{
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bool is_awoken = false;
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timer_obj_t *timer_obj = (timer_obj_t *)arg;
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if (timer_obj == NULL) {
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return;
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}
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if (timer_obj->timer_isr_fun.fn == NULL) {
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return;
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}
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TIMER_ENTER_CRITICAL(&timer_spinlock[timer_obj->timer_isr_fun.isr_timer_group]);
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{
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uint32_t intr_status = 0;
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timer_hal_get_intr_status(&(timer_obj->hal), &intr_status);
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if (intr_status & BIT(timer_obj->hal.idx)) {
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// Clear intrrupt status
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timer_hal_clear_intr_status(&(timer_obj->hal));
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uint64_t old_alarm_value = 0;
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timer_hal_get_alarm_value(&(timer_obj->hal), &old_alarm_value);
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// call user registered callback
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is_awoken = timer_obj->timer_isr_fun.fn(timer_obj->timer_isr_fun.args);
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// reenable alarm if required
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uint64_t new_alarm_value = 0;
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timer_hal_get_alarm_value(&(timer_obj->hal), &new_alarm_value);
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bool reenable_alarm = (new_alarm_value != old_alarm_value) || timer_hal_get_auto_reload(&timer_obj->hal);
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timer_hal_set_alarm_enable(&(timer_obj->hal), reenable_alarm);
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}
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}
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TIMER_EXIT_CRITICAL(&timer_spinlock[timer_obj->timer_isr_fun.isr_timer_group]);
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if (is_awoken) {
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portYIELD_FROM_ISR();
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}
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}
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esp_err_t timer_isr_callback_add(timer_group_t group_num, timer_idx_t timer_num, timer_isr_t isr_handler, void *args, int intr_alloc_flags)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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timer_disable_intr(group_num, timer_num);
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p_timer_obj[group_num][timer_num]->timer_isr_fun.fn = isr_handler;
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p_timer_obj[group_num][timer_num]->timer_isr_fun.args = args;
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p_timer_obj[group_num][timer_num]->timer_isr_fun.isr_timer_group = group_num;
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timer_isr_register(group_num, timer_num, timer_isr_default, (void *)p_timer_obj[group_num][timer_num],
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intr_alloc_flags, &(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle));
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timer_enable_intr(group_num, timer_num);
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return ESP_OK;
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}
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esp_err_t timer_isr_callback_remove(timer_group_t group_num, timer_idx_t timer_num)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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timer_disable_intr(group_num, timer_num);
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p_timer_obj[group_num][timer_num]->timer_isr_fun.fn = NULL;
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p_timer_obj[group_num][timer_num]->timer_isr_fun.args = NULL;
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esp_intr_free(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle);
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return ESP_OK;
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}
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esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num,
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void (*fn)(void *), void *arg, int intr_alloc_flags, timer_isr_handle_t *handle)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(fn != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
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int intr_source = 0;
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uint32_t status_reg = 0;
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uint32_t mask = 0;
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switch (group_num) {
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case TIMER_GROUP_0:
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default:
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if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE) == 0) {
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intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer_num;
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} else {
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intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer_num;
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}
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timer_hal_get_status_reg_mask_bit(&(p_timer_obj[TIMER_GROUP_0][timer_num]->hal), &status_reg, &mask);
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break;
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case TIMER_GROUP_1:
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if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE) == 0) {
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intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num;
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} else {
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intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer_num;
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}
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timer_hal_get_status_reg_mask_bit(&(p_timer_obj[TIMER_GROUP_1][timer_num]->hal), &status_reg, &mask);
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break;
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}
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return esp_intr_alloc_intrstatus(intr_source, intr_alloc_flags, status_reg, mask, fn, arg, handle);
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}
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esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer_config_t *config)
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(config != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(config->divider > 1 && config->divider < 65537, DIVIDER_RANGE_ERROR, ESP_ERR_INVALID_ARG);
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if (group_num == TIMER_GROUP_0) {
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periph_module_enable(PERIPH_TIMG0_MODULE);
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} else if (group_num == TIMER_GROUP_1) {
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periph_module_enable(PERIPH_TIMG1_MODULE);
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}
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if (p_timer_obj[group_num][timer_num] == NULL) {
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p_timer_obj[group_num][timer_num] = (timer_obj_t *) heap_caps_calloc(1, sizeof(timer_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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if (p_timer_obj[group_num][timer_num] == NULL) {
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ESP_LOGE(TIMER_TAG, "TIMER driver malloc error");
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return ESP_FAIL;
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}
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}
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TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
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timer_hal_init(&(p_timer_obj[group_num][timer_num]->hal), group_num, timer_num);
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timer_hal_intr_disable(&(p_timer_obj[group_num][timer_num]->hal));
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timer_hal_clear_intr_status(&(p_timer_obj[group_num][timer_num]->hal));
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timer_hal_set_auto_reload(&(p_timer_obj[group_num][timer_num]->hal), config->auto_reload);
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timer_hal_set_divider(&(p_timer_obj[group_num][timer_num]->hal), config->divider);
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timer_hal_set_counter_increase(&(p_timer_obj[group_num][timer_num]->hal), config->counter_dir);
|
|
timer_hal_set_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal), config->alarm_en);
|
|
if (config->intr_type == TIMER_INTR_LEVEL) {
|
|
timer_hal_set_level_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
|
|
}
|
|
// currently edge interrupt is not supported
|
|
// if (config->intr_type == TIMER_INTR_EDGE) {
|
|
// timer_hal_set_edge_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
|
|
// }
|
|
timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), config->counter_en);
|
|
#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
|
|
timer_hal_set_use_xtal(&(p_timer_obj[group_num][timer_num]->hal), config->clk_src);
|
|
#endif
|
|
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t timer_deinit(timer_group_t group_num, timer_idx_t timer_num)
|
|
{
|
|
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
|
|
|
|
TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
|
|
timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), TIMER_PAUSE);
|
|
timer_hal_intr_disable(&(p_timer_obj[group_num][timer_num]->hal));
|
|
timer_hal_clear_intr_status(&(p_timer_obj[group_num][timer_num]->hal));
|
|
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
|
|
|
|
heap_caps_free(p_timer_obj[group_num][timer_num]);
|
|
p_timer_obj[group_num][timer_num] = NULL;
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t timer_get_config(timer_group_t group_num, timer_idx_t timer_num, timer_config_t *config)
|
|
{
|
|
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(config != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
|
|
|
|
TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
|
|
config->alarm_en = timer_hal_get_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal));
|
|
config->auto_reload = timer_hal_get_auto_reload(&(p_timer_obj[group_num][timer_num]->hal));
|
|
config->counter_dir = timer_hal_get_counter_increase(&(p_timer_obj[group_num][timer_num]->hal));
|
|
config->counter_en = timer_hal_get_counter_enable(&(p_timer_obj[group_num][timer_num]->hal));
|
|
|
|
uint32_t div;
|
|
timer_hal_get_divider(&(p_timer_obj[group_num][timer_num]->hal), &div);
|
|
config->divider = div;
|
|
|
|
if (timer_hal_get_level_int_enable(&(p_timer_obj[group_num][timer_num]->hal))) {
|
|
config->intr_type = TIMER_INTR_LEVEL;
|
|
} else {
|
|
config->intr_type = TIMER_INTR_MAX;
|
|
}
|
|
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t timer_group_intr_enable(timer_group_t group_num, timer_intr_t en_mask)
|
|
{
|
|
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(p_timer_obj[group_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
|
|
for (int i = 0; i < TIMER_MAX; i++) {
|
|
if (en_mask & BIT(i)) {
|
|
timer_hal_intr_enable(&(p_timer_obj[group_num][i]->hal));
|
|
}
|
|
}
|
|
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t timer_group_intr_disable(timer_group_t group_num, timer_intr_t disable_mask)
|
|
{
|
|
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(p_timer_obj[group_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
|
|
for (int i = 0; i < TIMER_MAX; i++) {
|
|
if (disable_mask & BIT(i)) {
|
|
timer_hal_intr_disable(&(p_timer_obj[group_num][i]->hal));
|
|
}
|
|
}
|
|
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t timer_enable_intr(timer_group_t group_num, timer_idx_t timer_num)
|
|
{
|
|
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
|
|
timer_hal_intr_enable(&(p_timer_obj[group_num][timer_num]->hal));
|
|
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
|
|
{
|
|
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
|
|
timer_hal_intr_disable(&(p_timer_obj[group_num][timer_num]->hal));
|
|
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
|
|
return ESP_OK;
|
|
}
|
|
|
|
/* This function is deprecated */
|
|
timer_intr_t IRAM_ATTR timer_group_intr_get_in_isr(timer_group_t group_num)
|
|
{
|
|
uint32_t intr_raw_status = 0;
|
|
timer_hal_get_intr_raw_status(group_num, &intr_raw_status);
|
|
return intr_raw_status;
|
|
}
|
|
|
|
uint32_t IRAM_ATTR timer_group_get_intr_status_in_isr(timer_group_t group_num)
|
|
{
|
|
uint32_t intr_status = 0;
|
|
if (p_timer_obj[group_num][TIMER_0] != NULL) {
|
|
timer_hal_get_intr_status(&(p_timer_obj[group_num][TIMER_0]->hal), &intr_status);
|
|
} else if (p_timer_obj[group_num][TIMER_1] != NULL) {
|
|
timer_hal_get_intr_status(&(p_timer_obj[group_num][TIMER_1]->hal), &intr_status);
|
|
}
|
|
return intr_status;
|
|
}
|
|
|
|
/* This function is deprecated */
|
|
void IRAM_ATTR timer_group_intr_clr_in_isr(timer_group_t group_num, timer_idx_t timer_num)
|
|
{
|
|
timer_group_clr_intr_status_in_isr(group_num, timer_num);
|
|
}
|
|
|
|
void IRAM_ATTR timer_group_clr_intr_status_in_isr(timer_group_t group_num, timer_idx_t timer_num)
|
|
{
|
|
timer_hal_clear_intr_status(&(p_timer_obj[group_num][timer_num]->hal));
|
|
}
|
|
|
|
void IRAM_ATTR timer_group_enable_alarm_in_isr(timer_group_t group_num, timer_idx_t timer_num)
|
|
{
|
|
timer_hal_set_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
|
|
}
|
|
|
|
uint64_t IRAM_ATTR timer_group_get_counter_value_in_isr(timer_group_t group_num, timer_idx_t timer_num)
|
|
{
|
|
uint64_t val;
|
|
timer_hal_get_counter_value(&(p_timer_obj[group_num][timer_num]->hal), &val);
|
|
return val;
|
|
}
|
|
|
|
void IRAM_ATTR timer_group_set_alarm_value_in_isr(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_val)
|
|
{
|
|
timer_hal_set_alarm_value(&(p_timer_obj[group_num][timer_num]->hal), alarm_val);
|
|
}
|
|
|
|
void IRAM_ATTR timer_group_set_counter_enable_in_isr(timer_group_t group_num, timer_idx_t timer_num, timer_start_t counter_en)
|
|
{
|
|
timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), counter_en);
|
|
}
|
|
|
|
/* This function is deprecated */
|
|
void IRAM_ATTR timer_group_clr_intr_sta_in_isr(timer_group_t group_num, timer_intr_t intr_mask)
|
|
{
|
|
for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
|
|
if (intr_mask & BIT(timer_idx)) {
|
|
timer_group_clr_intr_status_in_isr(group_num, timer_idx);
|
|
}
|
|
}
|
|
}
|
|
|
|
bool IRAM_ATTR timer_group_get_auto_reload_in_isr(timer_group_t group_num, timer_idx_t timer_num)
|
|
{
|
|
return timer_hal_get_auto_reload(&(p_timer_obj[group_num][timer_num]->hal));
|
|
}
|
|
|
|
esp_err_t IRAM_ATTR timer_spinlock_take(timer_group_t group_num)
|
|
{
|
|
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t IRAM_ATTR timer_spinlock_give(timer_group_t group_num)
|
|
{
|
|
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
|
|
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
|
|
return ESP_OK;
|
|
}
|