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https://github.com/espressif/esp-idf.git
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182e937c5a
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
23 lines
548 B
C
23 lines
548 B
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/**
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* @file regi2c_bias.h
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* @brief Register definitions for bias
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*
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* This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
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* bootloader_hardware_init function in bootloader_esp32c6.c.
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*/
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#define I2C_BIAS 0X6A
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#define I2C_BIAS_HOSTID 0
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#define I2C_BIAS_DREG_1P1_PVT 1
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#define I2C_BIAS_DREG_1P1_PVT_MSB 3
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#define I2C_BIAS_DREG_1P1_PVT_LSB 0
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