mirror of
https://github.com/espressif/esp-idf.git
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638 lines
17 KiB
C
638 lines
17 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: configure_register */
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/** Type of store0 register
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* store the software massege0 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store0 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege0 in always-on field
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*/
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uint32_t lp_aon_store0:32;
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};
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uint32_t val;
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} lp_aon_store0_reg_t;
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/** Type of store1 register
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* store the software massege1 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store1 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege1 in always-on field
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*/
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uint32_t lp_aon_store1:32;
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};
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uint32_t val;
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} lp_aon_store1_reg_t;
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/** Type of store2 register
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* store the software massege2 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store2 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege2 in always-on field
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*/
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uint32_t lp_aon_store2:32;
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};
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uint32_t val;
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} lp_aon_store2_reg_t;
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/** Type of store3 register
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* store the software massege3 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store3 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege3 in always-on field
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*/
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uint32_t lp_aon_store3:32;
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};
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uint32_t val;
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} lp_aon_store3_reg_t;
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/** Type of store4 register
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* store the software massege4 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store4 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege4 in always-on field
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*/
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uint32_t lp_aon_store4:32;
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};
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uint32_t val;
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} lp_aon_store4_reg_t;
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/** Type of store5 register
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* store the software massege5 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store5 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege5 in always-on field
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*/
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uint32_t lp_aon_store5:32;
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};
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uint32_t val;
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} lp_aon_store5_reg_t;
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/** Type of store6 register
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* store the software massege6 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store6 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege6 in always-on field
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*/
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uint32_t lp_aon_store6:32;
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};
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uint32_t val;
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} lp_aon_store6_reg_t;
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/** Type of store7 register
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* store the software massege7 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store7 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege7 in always-on field
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*/
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uint32_t lp_aon_store7:32;
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};
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uint32_t val;
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} lp_aon_store7_reg_t;
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/** Type of store8 register
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* store the software massege8 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store8 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege8 in always-on field
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*/
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uint32_t lp_aon_store8:32;
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};
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uint32_t val;
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} lp_aon_store8_reg_t;
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/** Type of store9 register
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* store the software massege9 in always-on field
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*/
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typedef union {
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struct {
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/** lp_aon_store9 : R/W; bitpos: [31:0]; default: 0;
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* store the software massege9 in always-on field
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*/
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uint32_t lp_aon_store9:32;
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};
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uint32_t val;
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} lp_aon_store9_reg_t;
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/** Type of gpio_mux register
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* select the lp io controlled by hp iomux or lp iomux
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*/
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typedef union {
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struct {
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/** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0;
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* select the lp io 0~7 controlled by hp iomux or lp iomux
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* 1: controlled by lp iomux
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* 0: controlled by hp iomux
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*/
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uint32_t gpio_mux_sel:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_aon_gpio_mux_reg_t;
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/** Type of gpio_hold0 register
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* configure all io hold
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*/
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typedef union {
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struct {
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/** gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
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* configure io0~28 hold enable,when io in hold status, all io configure and output
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* will be latch , input function is useful
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*/
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uint32_t gpio_hold0:32;
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};
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uint32_t val;
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} lp_aon_gpio_hold0_reg_t;
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/** Type of gpio_hold1 register
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* reserved
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*/
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typedef union {
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struct {
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/** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
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* reserved
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*/
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uint32_t gpio_hold1:32;
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};
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uint32_t val;
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} lp_aon_gpio_hold1_reg_t;
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/** Type of sys_cfg register
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* configure system register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:29;
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/** force_download_boot_status : RO; bitpos: [29]; default: 0;
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* get force download mode status
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*/
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uint32_t force_download_boot_status:1;
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/** force_download_boot : R/W; bitpos: [30]; default: 0;
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* enable chip entry download mode or not
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* 1: enable
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* 0: no operation
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*/
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uint32_t force_download_boot:1;
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/** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
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* enable hp system reset by software or not
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* 1: reset
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* 0: no operation
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*/
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uint32_t hpsys_sw_reset:1;
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};
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uint32_t val;
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} lp_aon_sys_cfg_reg_t;
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/** Type of cpucore0_cfg register
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* configure core reset register
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*/
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typedef union {
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struct {
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/** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
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* enable cpu entry stall status
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* 0x86: entry stall status
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* Others : no operation
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*/
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uint32_t cpu_core0_sw_stall:8;
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uint32_t reserved_8:20;
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/** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0;
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* enable core reset by software
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* 1: reset
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* 0: no operation
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*/
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uint32_t cpu_core0_sw_reset:1;
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/** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
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* reserved
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*/
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uint32_t cpu_core0_ocd_halt_on_reset:1;
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/** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
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* configure core boot address
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* 1: ROM
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* 0: lp memory
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*/
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uint32_t cpu_core0_stat_vector_sel:1;
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/** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
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* disable bypass core dreset
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* 1: enable bypass
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* 0: disable bypass
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*/
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uint32_t cpu_core0_dreset_mask:1;
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};
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uint32_t val;
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} lp_aon_cpucore0_cfg_reg_t;
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/** Type of io_mux register
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* configure hp iomux reset bypass
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
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* bypass hp iomux reset from hp system reset event
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* 1: bypass
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* 0: no operation
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*/
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uint32_t io_mux_reset_disable:1;
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};
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uint32_t val;
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} lp_aon_io_mux_reg_t;
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/** Type of ext_wakeup_cntl register
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* configure alwayson external io wakeup
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*/
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typedef union {
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struct {
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/** ext_wakeup_status : RO; bitpos: [7:0]; default: 0;
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* get external wakeup status bitmap
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*/
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uint32_t ext_wakeup_status:8;
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uint32_t reserved_8:6;
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/** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0;
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* clear external wakeup status
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* 1: clear
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* 0: no operation
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*/
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uint32_t ext_wakeup_status_clr:1;
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/** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0;
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* enable io0~7 bit map use to external wakeup
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* 1: enable
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* 0: disable
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*/
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uint32_t ext_wakeup_sel:8;
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/** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0;
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* select external wakeup io level
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* 1: io high level wakeup
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* 0: io low level wakeup
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*/
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uint32_t ext_wakeup_lv:8;
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/** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
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* enable external filter or not
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* 1: enable
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* 0: disable
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*/
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uint32_t ext_wakeup_filter:1;
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};
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uint32_t val;
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} lp_aon_ext_wakeup_cntl_reg_t;
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/** Type of usb register
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* configure usb reset bypass
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** usb_reset_disable : R/W; bitpos: [31]; default: 0;
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* bypass usb reset from hp system reset event
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* 1: bypass
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* 0: no operation
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*/
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uint32_t usb_reset_disable:1;
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};
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uint32_t val;
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} lp_aon_usb_reg_t;
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/** Type of lpbus register
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* Select lp memory bus
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*/
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typedef union {
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struct {
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uint32_t reserved_0:28;
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/** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
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* get current lp memory bus fsm status
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*/
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uint32_t fast_mem_mux_fsm_idle:1;
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/** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
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* get current lp memory bus mode
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*/
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uint32_t fast_mem_mux_sel_status:1;
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/** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
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* enable reg_fast_mem_sel configure
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* 1: enable
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* 0: no operation
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*/
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uint32_t fast_mem_mux_sel_update:1;
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/** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
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* select lp memory bus is high speed mode or low speed mode
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* 1: high speed from hp system ahb
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* 0: low speed from lp system
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*/
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uint32_t fast_mem_mux_sel:1;
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};
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uint32_t val;
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} lp_aon_lpbus_reg_t;
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/** Type of sdio_active register
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* configure sdio act dnum
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*/
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typedef union {
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struct {
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uint32_t reserved_0:22;
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/** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
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* reserved
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*/
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uint32_t sdio_act_dnum:10;
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};
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uint32_t val;
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} lp_aon_sdio_active_reg_t;
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/** Type of lpcore register
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* configure etm wakeup register
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*/
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typedef union {
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struct {
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/** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
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* clear etm wakeup latch
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*/
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uint32_t lpcore_etm_wakeup_flag_clr:1;
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/** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
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* latch etmwakeup event
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*/
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uint32_t lpcore_etm_wakeup_flag:1;
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uint32_t reserved_2:29;
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/** lpcore_disable : R/W; bitpos: [31]; default: 0;
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* disable lp core
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* 1:disable
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* 0:no operation
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*/
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uint32_t lpcore_disable:1;
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};
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uint32_t val;
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} lp_aon_lpcore_reg_t;
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/** Type of sar_cct register
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* configure sar cct
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*/
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typedef union {
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struct {
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uint32_t reserved_0:29;
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/** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
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* configure sar cct
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*/
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uint32_t sar2_pwdet_cct:3;
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};
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uint32_t val;
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} lp_aon_sar_cct_reg_t;
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/** Type of modem_bus register
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* configure modem sync bridge
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** modem_sync_bridge_en : R/W; bitpos: [31]; default: 0;
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* enable modem sync bridge or not
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* 1: enable
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* 0: disable
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*/
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uint32_t modem_sync_bridge_en:1;
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};
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uint32_t val;
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} lp_aon_modem_bus_reg_t;
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/** Type of debug_sel0 register
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* reserved
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*/
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typedef union {
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struct {
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/** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0;
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* need des
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*/
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uint32_t lp_debug_sel0:7;
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/** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0;
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* need des
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*/
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uint32_t lp_debug_sel1:7;
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/** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0;
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* need des
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*/
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uint32_t lp_debug_sel2:7;
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/** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0;
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* need des
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*/
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uint32_t lp_debug_sel3:7;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} lp_aon_debug_sel0_reg_t;
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/** Type of debug_sel1 register
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* need des
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*/
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typedef union {
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struct {
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/** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0;
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* need des
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*/
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uint32_t lp_debug_sel4:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_aon_debug_sel1_reg_t;
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/** Type of backup_dma_cfg0 register
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* configure regdma always on register
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*/
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typedef union {
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struct {
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/** burst_limit_aon : R/W; bitpos: [4:0]; default: 10;
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* Set this field to configure max value of burst in signle transfer.
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*/
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uint32_t burst_limit_aon:5;
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/** read_interval_aon : R/W; bitpos: [11:5]; default: 10;
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* Set this field to configure read registers' interval time in reading mode.
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*/
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uint32_t read_interval_aon:7;
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/** branch_link_length_aon : R/W; bitpos: [15:12]; default: 0;
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* Set this field to configure link address.
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*/
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uint32_t branch_link_length_aon:4;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} lp_aon_backup_dma_cfg0_reg_t;
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/** Type of backup_dma_cfg1 register
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* configure regdma always on register
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*/
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typedef union {
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struct {
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/** link_wait_tout_thres_aon : R/W; bitpos: [9:0]; default: 100;
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* Set this field to configure the number of consecutive links of link list.
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*/
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uint32_t link_wait_tout_thres_aon:10;
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/** link_work_tout_thres_aon : R/W; bitpos: [19:10]; default: 100;
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* Set this field to configure maximum waiting time in waiting mode.
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*/
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uint32_t link_work_tout_thres_aon:10;
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/** link_backup_tout_thres_aon : R/W; bitpos: [29:20]; default: 100;
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* Set this field to configure maximum waiting time in backup mode.
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*/
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uint32_t link_backup_tout_thres_aon:10;
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uint32_t reserved_30:1;
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/** aon_bypass : R/W; bitpos: [31]; default: 0;
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* reserved
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*/
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uint32_t aon_bypass:1;
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};
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uint32_t val;
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} lp_aon_backup_dma_cfg1_reg_t;
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/** Type of backup_dma_cfg2 register
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* configure regdma always on register
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*/
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typedef union {
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struct {
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/** link_addr_aon : R/W; bitpos: [31:0]; default: 0;
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|
* Set this field to configure link address.
|
|
*/
|
|
uint32_t link_addr_aon:32;
|
|
};
|
|
uint32_t val;
|
|
} lp_aon_backup_dma_cfg2_reg_t;
|
|
|
|
/** Type of mem_ctrl register
|
|
* configure rmemory power in lp system register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** lp_mem_force_pd : R/W; bitpos: [0]; default: 0;
|
|
* force off lp memory
|
|
*/
|
|
uint32_t lp_mem_force_pd:1;
|
|
/** lp_mem_force_pu : R/W; bitpos: [1]; default: 1;
|
|
* force on lp memory
|
|
*/
|
|
uint32_t lp_mem_force_pu:1;
|
|
/** huk_mem_force_pd : R/W; bitpos: [2]; default: 1;
|
|
* force off huk memory
|
|
*/
|
|
uint32_t huk_mem_force_pd:1;
|
|
/** huk_mem_force_pu : R/W; bitpos: [3]; default: 0;
|
|
* force on huk memory
|
|
*/
|
|
uint32_t huk_mem_force_pu:1;
|
|
uint32_t reserved_4:28;
|
|
};
|
|
uint32_t val;
|
|
} lp_aon_mem_ctrl_reg_t;
|
|
|
|
/** Type of date register
|
|
* reserved
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** date : R/W; bitpos: [30:0]; default: 36774512;
|
|
* version register
|
|
*/
|
|
uint32_t date:31;
|
|
/** clk_en : R/W; bitpos: [31]; default: 0;
|
|
* version register
|
|
*/
|
|
uint32_t clk_en:1;
|
|
};
|
|
uint32_t val;
|
|
} lp_aon_date_reg_t;
|
|
|
|
|
|
/** Group: Configuration Register */
|
|
/** Type of spram_ctrl register
|
|
* configure lp memory power status
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
|
|
* configure lp memory power status
|
|
*/
|
|
uint32_t spram_mem_aux_ctrl:32;
|
|
};
|
|
uint32_t val;
|
|
} lp_aon_spram_ctrl_reg_t;
|
|
|
|
/** Type of sprf_ctrl register
|
|
* configure memory in lp system power status
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
|
|
* configure memory in lp system power status
|
|
*/
|
|
uint32_t sprf_mem_aux_ctrl:32;
|
|
};
|
|
uint32_t val;
|
|
} lp_aon_sprf_ctrl_reg_t;
|
|
|
|
|
|
typedef struct {
|
|
volatile lp_aon_store0_reg_t store0;
|
|
volatile lp_aon_store1_reg_t store1;
|
|
volatile lp_aon_store2_reg_t store2;
|
|
volatile lp_aon_store3_reg_t store3;
|
|
volatile lp_aon_store4_reg_t store4;
|
|
volatile lp_aon_store5_reg_t store5;
|
|
volatile lp_aon_store6_reg_t store6;
|
|
volatile lp_aon_store7_reg_t store7;
|
|
volatile lp_aon_store8_reg_t store8;
|
|
volatile lp_aon_store9_reg_t store9;
|
|
volatile lp_aon_gpio_mux_reg_t gpio_mux;
|
|
volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
|
|
volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
|
|
volatile lp_aon_sys_cfg_reg_t sys_cfg;
|
|
volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg;
|
|
volatile lp_aon_io_mux_reg_t io_mux;
|
|
volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
|
|
volatile lp_aon_usb_reg_t usb;
|
|
volatile lp_aon_lpbus_reg_t lpbus;
|
|
volatile lp_aon_sdio_active_reg_t sdio_active;
|
|
volatile lp_aon_lpcore_reg_t lpcore;
|
|
volatile lp_aon_sar_cct_reg_t sar_cct;
|
|
volatile lp_aon_modem_bus_reg_t modem_bus;
|
|
uint32_t reserved_05c;
|
|
volatile lp_aon_spram_ctrl_reg_t spram_ctrl;
|
|
volatile lp_aon_sprf_ctrl_reg_t sprf_ctrl;
|
|
volatile lp_aon_debug_sel0_reg_t debug_sel0;
|
|
volatile lp_aon_debug_sel1_reg_t debug_sel1;
|
|
volatile lp_aon_backup_dma_cfg0_reg_t backup_dma_cfg0;
|
|
volatile lp_aon_backup_dma_cfg1_reg_t backup_dma_cfg1;
|
|
volatile lp_aon_backup_dma_cfg2_reg_t backup_dma_cfg2;
|
|
volatile lp_aon_mem_ctrl_reg_t mem_ctrl;
|
|
uint32_t reserved_080[223];
|
|
volatile lp_aon_date_reg_t date;
|
|
} lp_aon_dev_t;
|
|
|
|
extern lp_aon_dev_t LP_AON;
|
|
|
|
#ifndef __cplusplus
|
|
_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
|
|
#endif
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|