mirror of
https://github.com/espressif/esp-idf.git
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388 lines
14 KiB
C
388 lines
14 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** LPPERI_CLK_EN_REG register
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* configure peri in lp system clk enable
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*/
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#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
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/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
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* lp rng clk enable
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* 1: enable clock
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* 0: disable clock
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*/
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#define LPPERI_RNG_CK_EN (BIT(24))
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#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S)
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#define LPPERI_RNG_CK_EN_V 0x00000001U
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#define LPPERI_RNG_CK_EN_S 24
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/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1;
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* lp optdebug clk enable
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* 1: enable clock
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* 0: disable clock
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*/
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#define LPPERI_OTP_DBG_CK_EN (BIT(25))
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#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S)
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#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U
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#define LPPERI_OTP_DBG_CK_EN_S 25
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/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1;
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* lp uart clk enable
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* 1: enable clock
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* 0: disable clock
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*/
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#define LPPERI_LP_UART_CK_EN (BIT(26))
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#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S)
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#define LPPERI_LP_UART_CK_EN_V 0x00000001U
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#define LPPERI_LP_UART_CK_EN_S 26
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/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1;
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* lp io clk enable
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* 1: enable clock
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* 0: disable clock
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*/
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#define LPPERI_LP_IO_CK_EN (BIT(27))
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#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S)
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#define LPPERI_LP_IO_CK_EN_V 0x00000001U
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#define LPPERI_LP_IO_CK_EN_S 27
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/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1;
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* lp ext i2c clk enable
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* 1: enable clock
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* 0: disable clock
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*/
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#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28))
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#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S)
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#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U
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#define LPPERI_LP_EXT_I2C_CK_EN_S 28
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/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1;
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* lp analog peri clk enable
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* 1: enable clock
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* 0: disable clock
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*/
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#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29))
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#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S)
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#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U
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#define LPPERI_LP_ANA_I2C_CK_EN_S 29
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/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1;
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* efuse core clk enable
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* 1: enable clock
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* 0: disable clock
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*/
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#define LPPERI_EFUSE_CK_EN (BIT(30))
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#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S)
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#define LPPERI_EFUSE_CK_EN_V 0x00000001U
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#define LPPERI_EFUSE_CK_EN_S 30
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/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0;
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* force on lp cpu clk enable
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* 1: enable cpu clock
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* 0: cpu clock is controlled by pmu
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*/
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#define LPPERI_LP_CPU_CK_EN (BIT(31))
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#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S)
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#define LPPERI_LP_CPU_CK_EN_V 0x00000001U
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#define LPPERI_LP_CPU_CK_EN_S 31
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/** LPPERI_RESET_EN_REG register
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* configure peri in lp system reset enable
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*/
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#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
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/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0;
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* lp bus reset enable
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* 1: enable reset
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* 0: disable reset
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*/
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#define LPPERI_BUS_RESET_EN (BIT(23))
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#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S)
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#define LPPERI_BUS_RESET_EN_V 0x00000001U
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#define LPPERI_BUS_RESET_EN_S 23
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/** LPPERI_LP_RNG_RESET_EN : R/W; bitpos: [24]; default: 0;
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* lp rng reset enable
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* 1: enable reset
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* 0: disable reset
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*/
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#define LPPERI_LP_RNG_RESET_EN (BIT(24))
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#define LPPERI_LP_RNG_RESET_EN_M (LPPERI_LP_RNG_RESET_EN_V << LPPERI_LP_RNG_RESET_EN_S)
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#define LPPERI_LP_RNG_RESET_EN_V 0x00000001U
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#define LPPERI_LP_RNG_RESET_EN_S 24
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/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0;
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* lp optdebug reset enable
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* 1: enable reset
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* 0: disable reset
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*/
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#define LPPERI_OTP_DBG_RESET_EN (BIT(25))
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#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S)
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#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U
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#define LPPERI_OTP_DBG_RESET_EN_S 25
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/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0;
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* lp uart reset enable
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* 1: enable reset
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* 0: disable reset
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*/
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#define LPPERI_LP_UART_RESET_EN (BIT(26))
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#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S)
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#define LPPERI_LP_UART_RESET_EN_V 0x00000001U
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#define LPPERI_LP_UART_RESET_EN_S 26
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/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0;
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* lp io reset enable
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* 1: enable reset
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* 0: disable reset
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*/
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#define LPPERI_LP_IO_RESET_EN (BIT(27))
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#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S)
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#define LPPERI_LP_IO_RESET_EN_V 0x00000001U
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#define LPPERI_LP_IO_RESET_EN_S 27
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/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0;
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* lp ext i2c reset enable
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* 1: enable reset
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* 0: disable reset
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*/
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#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28))
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#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S)
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#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U
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#define LPPERI_LP_EXT_I2C_RESET_EN_S 28
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/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0;
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* lp analog peri reset enable
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* 1: enable reset
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* 0: disable reset
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*/
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#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29))
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#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S)
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#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U
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#define LPPERI_LP_ANA_I2C_RESET_EN_S 29
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/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0;
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* efuse core reset enable
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* 1: enable reset
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* 0: disable reset
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*/
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#define LPPERI_EFUSE_RESET_EN (BIT(30))
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#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S)
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#define LPPERI_EFUSE_RESET_EN_V 0x00000001U
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#define LPPERI_EFUSE_RESET_EN_S 30
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/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0;
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* force on lp cpu reset enable
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* 1: enable cpu reset
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* 0: cpu reset is controlled by pmu
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*/
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#define LPPERI_LP_CPU_RESET_EN (BIT(31))
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#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S)
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#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U
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#define LPPERI_LP_CPU_RESET_EN_S 31
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/** LPPERI_RNG_DATA_REG register
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* RNG result register
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*/
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#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8)
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/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0;
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* get rng data
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*/
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#define LPPERI_RND_DATA 0xFFFFFFFFU
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#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S)
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#define LPPERI_RND_DATA_V 0xFFFFFFFFU
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#define LPPERI_RND_DATA_S 0
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/** LPPERI_CPU_REG register
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* configure lp cpu dbg enable
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*/
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#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
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/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1;
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* disable lp cpu dbg bus
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* 1: disable
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* 0: enable
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*/
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#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31))
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#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S)
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#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U
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#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31
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/** LPPERI_BUS_TIMEOUT_REG register
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* configure lp bus timeout
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*/
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#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10)
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/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535;
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* the timeout thres which bus access time, the timeout clk is lp_aon_fast
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*/
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#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU
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#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S)
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#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
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#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14
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/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0;
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* clear lp bus timeout interrupt
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*/
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#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30))
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#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S)
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#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
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#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30
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/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1;
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* enable lp bus timeout or not,when bus timeout, the ready will been force high by fsm
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* 1: enable
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* 0: disable
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*/
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#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31))
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#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S)
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#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
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#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31
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/** LPPERI_BUS_TIMEOUT_ADDR_REG register
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* the timeout address register
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*/
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#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14)
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/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
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* when bus timeout, this register will record the timeout address
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*/
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#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
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#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S)
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#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
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#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0
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/** LPPERI_BUS_TIMEOUT_UID_REG register
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* the timeout master id register
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*/
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#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18)
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/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
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* when bus timeout, this register will record the timeout master device
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*/
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#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU
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#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S)
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#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU
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#define LPPERI_LP_PERI_TIMEOUT_UID_S 0
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/** LPPERI_MEM_CTRL_REG register
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* configure uart memory power mode
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*/
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#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c)
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/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
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* clear uart wakeup latch
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* 1: clear
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* 0: no operation
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*/
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#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0))
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#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S)
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#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U
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#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0
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/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
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* latch uart wakeup event
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*/
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#define LPPERI_UART_WAKEUP_FLAG (BIT(1))
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#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S)
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#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U
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#define LPPERI_UART_WAKEUP_FLAG_S 1
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/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
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* enable uart wakeup not not
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*/
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#define LPPERI_UART_WAKEUP_EN (BIT(29))
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#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S)
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#define LPPERI_UART_WAKEUP_EN_V 0x00000001U
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#define LPPERI_UART_WAKEUP_EN_S 29
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/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
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* force off uart memory
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*/
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#define LPPERI_UART_MEM_FORCE_PD (BIT(30))
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#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S)
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#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U
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#define LPPERI_UART_MEM_FORCE_PD_S 30
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/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
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* force on uart memory
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*/
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#define LPPERI_UART_MEM_FORCE_PU (BIT(31))
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#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S)
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#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U
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#define LPPERI_UART_MEM_FORCE_PU_S 31
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/** LPPERI_INTERRUPT_SOURCE_REG register
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* record the lp cpu interrupt
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*/
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#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
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/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0;
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* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
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* lp_io_int
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*/
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#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU
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#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S)
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#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU
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#define LPPERI_LP_INTERRUPT_SOURCE_S 0
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/** LPPERI_RNG_CFG_REG register
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* configure rng register
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*/
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#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x24)
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/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
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* enable rng RO
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* 1: enable RO
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* 0: disable RO
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*/
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#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0))
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#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S)
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#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U
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#define LPPERI_RNG_SAMPLE_ENABLE_S 0
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/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255;
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* configure rng timer clk div
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*/
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#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU
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#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S)
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#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU
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#define LPPERI_RNG_TIMER_PSCALE_S 1
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/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1;
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* enable rng xor async rng timer
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*/
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#define LPPERI_RNG_TIMER_EN (BIT(9))
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#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S)
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#define LPPERI_RNG_TIMER_EN_V 0x00000001U
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#define LPPERI_RNG_TIMER_EN_S 9
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/** LPPERI_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3;
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* enable rng xor rtc timer:
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* bit(0) : enable rtc timer before crc
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* Bit(1): enable rtc timer after crc
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*/
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#define LPPERI_RTC_TIMER_EN 0x00000003U
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#define LPPERI_RTC_TIMER_EN_M (LPPERI_RTC_TIMER_EN_V << LPPERI_RTC_TIMER_EN_S)
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#define LPPERI_RTC_TIMER_EN_V 0x00000003U
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#define LPPERI_RTC_TIMER_EN_S 10
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/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
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* get rng RO sample cnt
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*/
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#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU
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#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S)
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#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU
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#define LPPERI_RNG_SAMPLE_CNT_S 24
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/** LPPERI_RNG_DATA_SYNC_REG register
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* rng result sync register
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*/
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#define LPPERI_RNG_DATA_SYNC_REG (DR_REG_LPPERI_BASE + 0x28)
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/** LPPERI_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0;
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* get rng sync result
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*/
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#define LPPERI_RND_SYNC_DATA 0xFFFFFFFFU
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#define LPPERI_RND_SYNC_DATA_M (LPPERI_RND_SYNC_DATA_V << LPPERI_RND_SYNC_DATA_S)
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#define LPPERI_RND_SYNC_DATA_V 0xFFFFFFFFU
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#define LPPERI_RND_SYNC_DATA_S 0
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/** LPPERI_DATE_REG register
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* version register
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*/
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#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
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/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 36774256;
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* version register
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*/
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#define LPPERI_LPPERI_DATE 0x7FFFFFFFU
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#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
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#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU
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#define LPPERI_LPPERI_DATE_S 0
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/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
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* force on reg clk
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*/
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#define LPPERI_CLK_EN (BIT(31))
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#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
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#define LPPERI_CLK_EN_V 0x00000001U
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#define LPPERI_CLK_EN_S 31
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#ifdef __cplusplus
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}
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#endif
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