mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
a1ba660b4a
The implicit promise of heap_alloc_caps() and friends is that the memory it returns is fit for the purpose as requested in the caps field. Before this commit, that did not happen; e.g. DMA-capable memory wass returned from a correct region, but not aligned/sized to something the DMA subsystem can handle. This commit adds an API to the esp_mm component that is then used by the heap component to adjust allocation alignment, caps and size dependent on the hardware requirement of the requested allocation caps.
627 lines
21 KiB
C
627 lines
21 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup cache_apis, cache operation related apis
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* @brief cache apis
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*/
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/** @addtogroup cache_apis
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* @{
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*/
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#define MIN_ICACHE_SIZE 16384
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#define MAX_ICACHE_SIZE 16384
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#define MIN_ICACHE_WAYS 8
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#define MAX_ICACHE_WAYS 8
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#define MAX_CACHE_WAYS 8
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#define MIN_CACHE_LINE_SIZE 32
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#define TAG_SIZE 4
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#define MIN_ICACHE_BANK_NUM 1
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#define MAX_ICACHE_BANK_NUM 1
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#define CACHE_MEMORY_BANK_NUM 1
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#define CACHE_MEMORY_IBANK_SIZE 0x4000
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#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE)
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#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE)
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#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE)
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#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE)
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typedef enum {
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CACHE_LOCK_LOCK = BIT(0),
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CACHE_LOCK_UNLOCK = BIT(1),
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} cache_lock_t;
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typedef enum {
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CACHE_SYNC_INVALIDATE = BIT(0),
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CACHE_SYNC_CLEAN = BIT(1),
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CACHE_SYNC_WRITEBACK = BIT(2),
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CACHE_SYNC_WRITEBACK_INVALIDATE = BIT(3),
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} cache_sync_t;
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typedef enum {
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CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */
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CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */
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} cache_size_t;
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typedef enum {
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CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */
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CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */
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} cache_ways_t;
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typedef enum {
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CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */
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CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */
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CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */
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} cache_line_size_t;
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typedef enum {
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CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */
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CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */
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} cache_autoload_order_t;
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#define CACHE_AUTOLOAD_STEP(i) ((i) - 1)
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typedef enum {
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CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */
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CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */
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CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */
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} cache_autoload_trigger_t;
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typedef enum {
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CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/
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CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */
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} cache_freeze_mode_t;
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typedef enum {
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MMU_PAGE_MODE_64KB = 0,
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MMU_PAGE_MODE_32KB = 1,
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MMU_PAGE_MODE_16KB = 2,
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MMU_PAGE_MODE_8KB = 3,
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MMU_PAGE_MODE_INVALID,
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} mmu_page_mode_t;
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struct cache_mode {
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uint32_t cache_size; /*!< cache size in byte */
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uint16_t cache_line_size; /*!< cache line size in byte */
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uint8_t cache_ways; /*!< cache ways, always 4 */
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uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */
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};
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struct icache_tag_item {
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uint32_t valid:1; /*!< the tag item is valid or not */
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uint32_t lock:1; /*!< the cache line is locked or not */
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uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */
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uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */
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uint32_t reserved:14;
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};
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struct autoload_config {
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uint8_t order; /*!< autoload step is positive or negative */
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uint8_t trigger; /*!< autoload trigger */
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uint8_t ena0; /*!< autoload region0 enable */
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uint8_t ena1; /*!< autoload region1 enable */
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uint32_t addr0; /*!< autoload region0 start address */
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uint32_t size0; /*!< autoload region0 size */
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uint32_t addr1; /*!< autoload region1 start address */
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uint32_t size1; /*!< autoload region1 size */
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};
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struct tag_group_info {
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struct cache_mode mode; /*!< cache and cache mode */
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uint32_t filter_addr; /*!< the address that used to generate the struct */
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uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */
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uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */
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uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */
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};
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struct lock_config {
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uint32_t addr; /*!< manual lock address*/
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uint16_t size; /*!< manual lock size*/
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uint16_t group; /*!< manual lock group, 0 or 1*/
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};
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struct cache_internal_stub_table {
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uint32_t (* cache_line_size)(void);
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uint32_t (* cache_addr)(uint32_t addr);
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void (* sync_cache_items)(uint32_t type, uint32_t addr, uint32_t items);
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void (* lock_cache_items)(uint32_t lock, uint32_t addr, uint32_t items);
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uint32_t (* suspend_cache_autoload)(void);
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void (* resume_cache_autoload)(uint32_t autoload);
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void (* freeze_cache_enable)(cache_freeze_mode_t mode);
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void (* freeze_cache_disable)(void);
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int (* op_addr)(uint32_t op_type,
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uint32_t start_addr,
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uint32_t size,
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uint32_t cache_line_size,
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uint32_t max_sync_num,
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void(* cache_Iop)(uint32_t, uint32_t, uint32_t));
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};
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/* Defined in the interface file, default value is rom_default_cache_internal_table */
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extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr;
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typedef void (* cache_op_start)(void);
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typedef void (* cache_op_end)(void);
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typedef struct {
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cache_op_start start;
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cache_op_end end;
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} cache_op_cb_t;
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/* Defined in the interface file, default value is NULL */
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extern const cache_op_cb_t* rom_cache_op_cb;
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#define ESP_ROM_ERR_INVALID_ARG 1
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#define MMU_SET_ADDR_ALIGNED_ERROR 2
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#define MMU_SET_PASE_SIZE_ERROR 3
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#define MMU_SET_VADDR_OUT_RANGE 4
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#define CACHE_OP_ICACHE_Y 1
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#define CACHE_OP_ICACHE_N 0
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/**
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* @brief Initialise cache mmu, mark all entries as invalid.
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* Please do not call this function in your SDK application.
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*
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* @param None
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*
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* @return None
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*/
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void Cache_MMU_Init(void);
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/**
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* @brief Init Cache for ROM boot, including resetting the Icache, initializing MMU, Enabling ICache, unmasking bus.
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*
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* @param None
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*
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* @return None
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*/
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void ROM_Boot_Cache_Init(void);
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/**
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* @brief Set ICache mmu mapping.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t senitive : Config this page should apply flash encryption or not
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*
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* @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
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* esp32c61, external memory is always flash
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*
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* @param uint32_t vaddr : virtual address in CPU address space.
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* Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address.
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* Should be aligned by psize.
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*
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* @param uint32_t paddr : physical address in external memory.
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* Should be aligned by psize.
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*
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* @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here.
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*
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* @param uint32_t num : pages to be set.
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*
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* @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
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*
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* @return uint32_t: error status
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* 0 : mmu set success
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* 2 : vaddr or paddr is not aligned
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* 3 : psize error
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* 4 : vaddr is out of range
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*/
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int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
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/**
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* @brief Set DCache mmu mapping.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
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* esp32c61, external memory is always flash
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*
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* @param uint32_t vaddr : virtual address in CPU address space.
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* Can be DRam0, DRam1, DRom0, DPort and AHB buses address.
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* Should be aligned by psize.
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*
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* @param uint32_t paddr : physical address in external memory.
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* Should be aligned by psize.
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*
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* @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here.
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*
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* @param uint32_t num : pages to be set.
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* @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
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*
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* @return uint32_t: error status
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* 0 : mmu set success
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* 2 : vaddr or paddr is not aligned
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* 3 : psize error
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* 4 : vaddr is out of range
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*/
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int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
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/**
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* @brief Get cache mode of ICache or DCache.
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* Please do not call this function in your SDK application.
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*
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* @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field
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*
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* return none
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*/
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void Cache_Get_Mode(struct cache_mode * mode);
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/**
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* @brief Set cache page mode.
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*
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* @param mmu_page_mode_t
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*
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* @return None
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*/
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void MMU_Set_Page_Mode(mmu_page_mode_t pg_mode);
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/**
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* @brief Get cache page mode.
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*
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* @param None
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*
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* @return page mode
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*/
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mmu_page_mode_t MMU_Get_Page_Mode(void);
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/**
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* @brief Invalidate the cache items for ICache.
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* Operation will be done CACHE_LINE_SIZE aligned.
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* If the region is not in ICache addr room, nothing will be done.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t addr: start address to invalidate
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*
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* @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
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*
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* @return None
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*/
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void Cache_Sync_Items(uint32_t type, uint32_t addr, uint32_t bytes);
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/**
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* @brief Invalidate the Cache items in the region from ICache or DCache.
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* If the region is not in Cache addr room, nothing will be done.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t addr : invalidated region start address.
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*
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* @param uint32_t size : invalidated region size.
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*
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* @return 0 for success
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* 1 for invalid argument
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*/
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int Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
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int Cache_Clean_Addr(uint32_t addr, uint32_t size);
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int Cache_WriteBack_Addr(uint32_t addr, uint32_t size);
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int Cache_WriteBack_Invalidate_Addr(uint32_t addr, uint32_t size);
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/**
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* @brief Invalidate all cache items in ICache.
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* Please do not call this function in your SDK application.
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*
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* @param None
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*
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* @return None
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*/
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void Cache_Invalidate_All(void);
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void Cache_Clean_All(void);
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void Cache_WriteBack_All(void);
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void Cache_WriteBack_Invalidate_All(void);
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/**
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* @brief Mask all buses through ICache and DCache.
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* Please do not call this function in your SDK application.
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*
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* @param None
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*
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* @return None
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*/
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void Cache_Mask_All(void);
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/**
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* @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations.
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* Please do not call this function in your SDK application.
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*
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* @param None
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*
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* @return uint32_t : 0 for ICache not auto preload before suspend.
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*/
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uint32_t Cache_Suspend_Autoload(void);
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/**
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* @brief Resume ICache auto preload operation after some ICache operations.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t autoload : 0 for ICache not auto preload before suspend.
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*
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* @return None.
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*/
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void Cache_Resume_Autoload(uint32_t autoload);
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/**
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* @brief Start an ICache manual preload, will suspend auto preload of ICache.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t addr : start address of the preload region.
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*
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* @param uint32_t size : size of the preload region, should not exceed the size of ICache.
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*
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* @param uint32_t order : the preload order, 0 for positive, other for negative
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*
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* @return uint32_t : 0 for ICache not auto preload before manual preload.
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*/
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uint32_t Cache_Start_Preload(uint32_t addr, uint32_t size, uint32_t order);
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/**
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* @brief Return if the ICache manual preload done.
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* Please do not call this function in your SDK application.
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*
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* @param None
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*
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* @return uint32_t : 0 for ICache manual preload not done.
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*/
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uint32_t Cache_Preload_Done(void);
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/**
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* @brief End the ICache manual preload to resume auto preload of ICache.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t autoload : 0 for ICache not auto preload before manual preload.
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*
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* @return None
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*/
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void Cache_End_Preload(uint32_t autoload);
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/**
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* @brief Config autoload parameters of ICache.
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* Please do not call this function in your SDK application.
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*
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* @param struct autoload_config * config : autoload parameters.
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*
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* @return None
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*/
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void Cache_Config_Autoload(const struct autoload_config * config);
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/**
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* @brief Enable auto preload for ICache.
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* Please do not call this function in your SDK application.
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*
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* @param None
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*
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* @return None
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*/
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void Cache_Enable_Autoload(void);
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/**
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* @brief Disable auto preload for ICache.
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* Please do not call this function in your SDK application.
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*
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* @param None
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*
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* @return None
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*/
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void Cache_Disable_Autoload(void);
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/**
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* @brief Config a group of prelock parameters of ICache.
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* Please do not call this function in your SDK application.
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*
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* @param struct lock_config * config : a group of lock parameters.
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*
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* @return None
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*/
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void Cache_Enable_PreLock(const struct lock_config *config);
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/**
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* @brief Disable a group of prelock parameters for ICache.
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* However, the locked data will not be released.
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* Please do not call this function in your SDK application.
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*
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* @param uint16_t group : 0 for group0, 1 for group1.
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*
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* @return None
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*/
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void Cache_Disable_PreLock(uint16_t group);
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/**
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* @brief Lock the cache items for ICache.
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* Operation will be done CACHE_LINE_SIZE aligned.
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* If the region is not in ICache addr room, nothing will be done.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t addr: start address to lock
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*
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* @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
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*
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* @return None
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*/
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int Cache_Lock_Items(uint32_t lock, uint32_t addr, uint32_t items);
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/**
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* @brief Lock the cache items in tag memory for ICache or DCache.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t addr : start address of lock region.
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*
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* @param uint32_t size : size of lock region.
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*
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* @return 0 for success
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* 1 for invalid argument
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*/
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int Cache_Lock_Addr(uint32_t addr, uint32_t size);
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/**
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* @brief Unlock the cache items in tag memory for ICache or DCache.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t addr : start address of unlock region.
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*
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* @param uint32_t size : size of unlock region.
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*
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* @return 0 for success
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* 1 for invalid argument
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*/
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int Cache_Unlock_Addr(uint32_t addr, uint32_t size);
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/**
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* @brief Disable ICache access for the cpu.
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* This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle.
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* Please do not call this function in your SDK application.
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*
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* @return uint32_t : auto preload enabled before
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*/
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uint32_t Cache_Disable_Cache(void);
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/**
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* @brief Enable ICache access for the cpu.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t autoload : ICache will preload then.
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*
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* @return None
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*/
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void Cache_Enable_Cache(uint32_t autoload);
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/**
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* @brief Suspend ICache access for the cpu.
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* The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle.
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* Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case).
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* Please do not call this function in your SDK application.
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*
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* @param None
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*
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* @return uint32_t : auto preload enabled before
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*/
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uint32_t Cache_Suspend_Cache(void);
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/**
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* @brief Resume ICache access for the cpu.
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* Please do not call this function in your SDK application.
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*
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* @param uint32_t autoload : ICache will preload then.
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*
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* @return None
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*/
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void Cache_Resume_Cache(uint32_t autoload);
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/**
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* @brief Get ICache cache line size
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*
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* @param None
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*
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* @return uint32_t: 16, 32, 64 Byte
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|
*/
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uint32_t Cache_Get_Line_Size(void);
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/**
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|
* @brief Enable freeze for ICache.
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|
* Any miss request will be rejected, including cpu miss and preload/autoload miss.
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|
* Please do not call this function in your SDK application.
|
|
*
|
|
* @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit
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|
*
|
|
* @return None
|
|
*/
|
|
void Cache_Freeze_Enable(cache_freeze_mode_t mode);
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|
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/**
|
|
* @brief Disable freeze for ICache.
|
|
* Please do not call this function in your SDK application.
|
|
*
|
|
* @return None
|
|
*/
|
|
void Cache_Freeze_Disable(void);
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|
|
/**
|
|
* @brief Travel tag memory to run a call back function.
|
|
* ICache and DCache are suspend when doing this.
|
|
* The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
|
|
* Please do not call this function in your SDK application.
|
|
*
|
|
* @param struct cache_mode * mode : the cache to check and the cache mode.
|
|
*
|
|
* @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function.
|
|
* 0 for do not filter, all cache lines will be returned.
|
|
*
|
|
* @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time.
|
|
*
|
|
* @return None
|
|
*/
|
|
void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *));
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|
|
|
/**
|
|
* @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways.
|
|
* Please do not call this function in your SDK application.
|
|
*
|
|
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
|
|
*
|
|
* @param uint32_t tag : the tag part of a tag item, 12-14 bits.
|
|
*
|
|
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
|
|
*
|
|
* @return uint32_t : the virtual address.
|
|
*/
|
|
uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @brief Get the cache MMU IROM end address.
|
|
* Please do not call this function in your SDK application.
|
|
*
|
|
* @param void
|
|
*
|
|
* @return uint32_t : the word value of the address.
|
|
*/
|
|
uint32_t Cache_Get_IROM_MMU_End(void);
|
|
|
|
/**
|
|
* @brief Get the cache MMU DROM end address.
|
|
* Please do not call this function in your SDK application.
|
|
*
|
|
* @param void
|
|
*
|
|
* @return uint32_t : the word value of the address.
|
|
*/
|
|
uint32_t Cache_Get_DROM_MMU_End(void);
|
|
|
|
/**
|
|
* @brief Configure cache MMU page size according to instruction and rodata size
|
|
*
|
|
* @param irom_size The instruction cache MMU page size
|
|
* @param drom_size The rodata data cache MMU page size
|
|
*/
|
|
void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
|
|
|
|
uint32_t Cache_Count_Flash_Pages(uint32_t * page0_mapped);
|
|
|
|
uint32_t Cache_Flash_To_SPIRAM_Copy(uint32_t bus_start_addr, uint32_t start_page, uint32_t * page0_page);
|
|
|
|
#define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \
|
|
Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|