mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
ef10c2576f
The remaining 4 kB had been reserved for storing RF calibration and
BT stack state since 4e092be6. However, these features never got
implemented. If we ever need to place RF related data into RTC slow
memory, we can do this by creating a variable with RTC_NOINIT_ATTR
instead.
Closes https://github.com/espressif/esp-idf/issues/3993
221 lines
7.2 KiB
C
221 lines
7.2 KiB
C
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _ROM_RTC_H_
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#define _ROM_RTC_H_
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#include "ets_sys.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/rtc_cntl_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup rtc_apis, rtc registers and memory related apis
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* @brief rtc apis
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*/
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/** @addtogroup rtc_apis
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* @{
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*/
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/**************************************************************************************
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* Note: *
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* Some Rtc memory and registers are used, in ROM or in internal library. *
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* Please do not use reserved or used rtc memory or registers. *
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* *
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*************************************************************************************
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* RTC Memory & Store Register usage
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*************************************************************************************
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* rtc memory addr type size usage
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* 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
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* 0x3ff61000+SIZE_CP Slow 8192-SIZE_CP
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*
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* 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
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*
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*************************************************************************************
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* RTC store registers usage
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* RTC_CNTL_STORE0_REG Reserved
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* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
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* RTC_CNTL_STORE2_REG Boot time, low word
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* RTC_CNTL_STORE3_REG Boot time, high word
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* RTC_CNTL_STORE4_REG External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
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* RTC_CNTL_STORE5_REG APB bus frequency
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* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
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* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
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*************************************************************************************
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*/
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#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
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#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
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#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
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#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
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#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
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#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
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#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
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#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
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#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
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typedef enum {
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AWAKE = 0, //<CPU ON
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LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
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DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
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} SLEEP_MODE;
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typedef enum {
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NO_MEAN = 0,
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POWERON_RESET = 1, /**<1, Vbat power on reset*/
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SW_RESET = 3, /**<3, Software reset digital core*/
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OWDT_RESET = 4, /**<4, Legacy watch dog reset digital core*/
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DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
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SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/
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TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
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TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
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RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
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INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
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TGWDT_CPU_RESET = 11, /**<11, Time Group reset CPU*/
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SW_CPU_RESET = 12, /**<12, Software reset CPU*/
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RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
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EXT_CPU_RESET = 14, /**<14, for APP CPU, reseted by PRO CPU*/
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RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
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RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
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} RESET_REASON;
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typedef enum {
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NO_SLEEP = 0,
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EXT_EVENT0_TRIG = BIT0,
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EXT_EVENT1_TRIG = BIT1,
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GPIO_TRIG = BIT2,
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TIMER_EXPIRE = BIT3,
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SDIO_TRIG = BIT4,
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MAC_TRIG = BIT5,
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UART0_TRIG = BIT6,
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UART1_TRIG = BIT7,
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TOUCH_TRIG = BIT8,
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SAR_TRIG = BIT9,
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BT_TRIG = BIT10
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} WAKEUP_REASON;
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typedef enum {
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DISEN_WAKEUP = NO_SLEEP,
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EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
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EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
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GPIO_TRIG_EN = GPIO_TRIG,
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TIMER_EXPIRE_EN = TIMER_EXPIRE,
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SDIO_TRIG_EN = SDIO_TRIG,
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MAC_TRIG_EN = MAC_TRIG,
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UART0_TRIG_EN = UART0_TRIG,
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UART1_TRIG_EN = UART1_TRIG,
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TOUCH_TRIG_EN = TOUCH_TRIG,
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SAR_TRIG_EN = SAR_TRIG,
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BT_TRIG_EN = BT_TRIG
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} WAKEUP_ENABLE;
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typedef enum {
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NO_INT = 0,
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WAKEUP_INT = BIT0,
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REJECT_INT = BIT1,
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SDIO_IDLE_INT = BIT2,
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RTC_WDT_INT = BIT3,
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RTC_TIME_VALID_INT = BIT4
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} RTC_INT_REASON;
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typedef enum {
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DISEN_INT = 0,
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WAKEUP_INT_EN = WAKEUP_INT,
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REJECT_INT_EN = REJECT_INT,
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SDIO_IDLE_INT_EN = SDIO_IDLE_INT,
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RTC_WDT_INT_EN = RTC_WDT_INT,
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RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
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} RTC_INT_EN;
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/**
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* @brief Get the reset reason for CPU.
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*
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* @param int cpu_no : CPU no.
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*
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* @return RESET_REASON
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*/
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RESET_REASON rtc_get_reset_reason(int cpu_no);
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/**
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* @brief Get the wakeup cause for CPU.
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*
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* @param int cpu_no : CPU no.
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*
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* @return WAKEUP_REASON
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*/
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WAKEUP_REASON rtc_get_wakeup_cause(void);
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/**
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* @brief Get CRC for Fast RTC Memory.
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*
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* @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
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*
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* @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
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*
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* @return uint32_t : CRC32 result
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*/
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uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
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/**
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* @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
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*
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* @param None
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*
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* @return None
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*/
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void set_rtc_memory_crc(void);
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/**
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* @brief Software Reset digital core.
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*
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* It is not recommended to use this function in esp-idf, use
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* esp_restart() instead.
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*
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* @param None
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*
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* @return None
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*/
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void __attribute__((noreturn)) software_reset(void);
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/**
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* @brief Software Reset digital core.
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*
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* It is not recommended to use this function in esp-idf, use
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* esp_restart() instead.
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*
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* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
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*
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* @return None
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*/
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void software_reset_cpu(int cpu_no);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_RTC_H_ */
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