mirror of
https://github.com/espressif/esp-idf.git
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156 lines
5.8 KiB
C
156 lines
5.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define NLBITS 3
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#define CLIC_EXT_INTR_NUM_OFFSET 16
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#define DR_REG_CLIC_BASE (0x20800000)
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#define DR_REG_CLIC_CTRL_BASE (0x20801000)
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#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0)
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/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */
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/*description: .*/
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#define CLIC_INT_CONFIG_NMBITS 0x00000003
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#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V) << (CLIC_INT_CONFIG_NMBITS_S))
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#define CLIC_INT_CONFIG_NMBITS_V 0x3
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#define CLIC_INT_CONFIG_NMBITS_S 5
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/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
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/*description: .*/
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#define CLIC_INT_CONFIG_NLBITS 0x0000000F
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#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V) << (CCLIC_INT_CONFIG_NLBITS_S))
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#define CLIC_INT_CONFIG_NLBITS_V 0xF
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#define CLIC_INT_CONFIG_NLBITS_S 1
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/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */
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/*description: .*/
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#define CLIC_INT_CONFIG_NVBITS (BIT(0))
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#define CLIC_INT_CONFIG_NVBITS_M (BIT(0))
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#define CLIC_INT_CONFIG_NVBITS_V 0x1
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#define CLIC_INT_CONFIG_NVBITS_S 0
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#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4)
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/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
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/*description: .*/
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#define CLIC_INT_INFO_CTLBITS 0x0000000F
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#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V) << (CLIC_INT_INFO_CTLBITS_S))
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#define CLIC_INT_INFO_CTLBITS_V 0xF
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#define CLIC_INT_INFO_CTLBITS_S 21
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/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */
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/*description: .*/
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#define CLIC_INT_INFO_VERSION 0x000000FF
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#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V) << (CLIC_INT_INFO_VERSION_S))
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#define CLIC_INT_INFO_VERSION_V 0xFF
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#define CLIC_INT_INFO_VERSION_S 13
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/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */
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/*description: .*/
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#define CLIC_INT_INFO_NUM_INT 0x00001FFF
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#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V) << (CLIC_INT_INFO_NUM_INT_S))
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#define CLIC_INT_INFO_NUM_INT_V 0x1FFF
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#define CLIC_INT_INFO_NUM_INT_S 0
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#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8)
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/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
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/*description: .*/
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#define CLIC_CPU_INT_THRESH 0x000000FF
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#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V) << (CLIC_CPU_INT_THRESH_S))
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#define CLIC_CPU_INT_THRESH_V 0xFF
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#define CLIC_CPU_INT_THRESH_S 24
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#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i)*4)
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/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
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/*description: .*/
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#define CLIC_INT_CTL 0x000000FF
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#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V) << (CLIC_INT_CTL_S))
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#define CLIC_INT_CTL_V 0xFF
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#define CLIC_INT_CTL_S 24
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/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
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/*description: .*/
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#define CLIC_INT_ATTR_MODE 0x00000003
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#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V) << (CLIC_INT_ATTR_MODE_S))
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#define CLIC_INT_ATTR_MODE_V 0x3
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#define CLIC_INT_ATTR_MODE_S 22
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/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
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/*description: .*/
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#define CLIC_INT_ATTR_TRIG 0x00000003
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#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V) << (CLIC_INT_ATTR_TRIG_S))
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#define CLIC_INT_ATTR_TRIG_V 0x3
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#define CLIC_INT_ATTR_TRIG_S 17
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/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */
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/*description: .*/
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#define CLIC_INT_ATTR_SHV (BIT(16))
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#define CLIC_INT_ATTR_SHV_M (BIT(16))
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#define CLIC_INT_ATTR_SHV_V 0x1
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#define CLIC_INT_ATTR_SHV_S 16
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/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
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/*description: .*/
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#define CLIC_INT_IE (BIT(8))
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#define CLIC_INT_IE_M (BIT(8))
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#define CLIC_INT_IE_V 0x1
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#define CLIC_INT_IE_S 8
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/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: .*/
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#define CLIC_INT_IP (BIT(0))
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#define CLIC_INT_IP_M (BIT(0))
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#define CLIC_INT_IP_V 0x1
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#define CLIC_INT_IP_S 0
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// each of following registers are 8bits
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#define BYTE_CLIC_INT_IP_REG(i) (DR_REG_CLIC_CTRL_BASE + (i)*4)
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/* BYTE_CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: .*/
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#define BYTE_CLIC_INT_IP (BIT(0))
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#define BYTE_CLIC_INT_IP_M (BIT(0))
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#define BYTE_CLIC_INT_IP_V 0x1
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#define BYTE_CLIC_INT_IP_S 0
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#define BYTE_CLIC_INT_IE_REG(i) (DR_REG_CLIC_CTRL_BASE + 1 + (i)*4)
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/* BYTE_CLIC_INT_IE : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: .*/
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#define BYTE_CLIC_INT_IE (BIT(0))
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#define BYTE_CLIC_INT_IE_M (BIT(0))
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#define BYTE_CLIC_INT_IE_V 0x1
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#define BYTE_CLIC_INT_IE_S 0
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#define BYTE_CLIC_INT_ATTR_REG(i) (DR_REG_CLIC_CTRL_BASE + 2 + (i)*4)
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/* BYTE_CLIC_INT_ATTR_SHV : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: 1 means hardware vector interrupt.*/
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#define BYTE_CLIC_INT_ATTR_SHV (BIT(0))
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#define BYTE_CLIC_INT_ATTR_SHV_M (BIT(0))
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#define BYTE_CLIC_INT_ATTR_SHV_V 0x1
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#define BYTE_CLIC_INT_ATTR_SHV_S 0
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/* BYTE_CLIC_INT_ATTR_TRIG: R/W ; bitpos:[2:1] ;default: 2'd0 ; */
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/*description:
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[X0] -> level trigger
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[01] -> rising edge trigger
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[11] -> falling edge trigger */
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#define BYTE_CLIC_INT_ATTR_TRIG 0x00000003
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#define BYTE_CLIC_INT_ATTR_TRIG_M ((BYTE_CLIC_INT_ATTR_TRIG_V) << (BYTE_CLIC_INT_ATTR_TRIG_S))
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#define BYTE_CLIC_INT_ATTR_TRIG_V 0x3
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#define BYTE_CLIC_INT_ATTR_TRIG_S 1
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/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:6] ;default: 2'd0 ; */
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/*description: privilege level for interrupt, fixed to 2'b11 */
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#define BYTE_CLIC_INT_ATTR_MODE 0x00000003
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#define BYTE_CLIC_INT_ATTR_MODE_M ((BYTE_CLIC_INT_ATTR_MODE_V) << (BYTE_CLIC_INT_ATTR_MODE_S))
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#define BYTE_CLIC_INT_ATTR_MODE_V 0x3
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#define BYTE_CLIC_INT_ATTR_MODE_S 6
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#define BYTE_CLIC_INT_CTL_REG(i) (DR_REG_CLIC_CTRL_BASE + 3 + (i)*4)
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/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:5] ;default: 3'd0 ; */
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/*description: interrupt priority */
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#define BYTE_CLIC_INT_CTL 0x00000007
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#define BYTE_CLIC_INT_CTL_M ((BYTE_CLIC_INT_CTL_V) << (BYTE_CLIC_INT_CTL_S))
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#define BYTE_CLIC_INT_CTL_V 0x7
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#define BYTE_CLIC_INT_CTL_S 5
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#ifdef __cplusplus
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}
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#endif
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