esp-idf/components/esp_system/Kconfig
Martin Vychodil 69096ddce5 Security: ESP32C3 memory protection feature (IRAM0/DRAM0)
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)

Closes https://jira.espressif.com:8443/browse/IDF-2092
2021-01-27 08:44:03 +01:00

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menu "ESP System Settings"
choice ESP_SYSTEM_PANIC
prompt "Panic handler behaviour"
default ESP_SYSTEM_PANIC_PRINT_REBOOT
help
If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
invoked. Configure the panic handler's action here.
config ESP_SYSTEM_PANIC_PRINT_HALT
bool "Print registers and halt"
help
Outputs the relevant registers over the serial port and halt the
processor. Needs a manual reset to restart.
config ESP_SYSTEM_PANIC_PRINT_REBOOT
bool "Print registers and reboot"
help
Outputs the relevant registers over the serial port and immediately
reset the processor.
config ESP_SYSTEM_PANIC_SILENT_REBOOT
bool "Silent reboot"
help
Just resets the processor without outputting anything
config ESP_SYSTEM_PANIC_GDBSTUB
bool "Invoke GDBStub"
select ESP_GDBSTUB_ENABLED
help
Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
of the crash.
endchoice
config ESP_SYSTEM_SINGLE_CORE_MODE
bool
default n
help
Only initialize and use the main core.
config ESP_SYSTEM_RTC_EXT_XTAL
# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
# e.g. It will be selected on when ESP32_RTC_CLK_SRC_EXT_CRYS is on
bool
default n
config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
int "Bootstrap cycles for external 32kHz crystal"
depends on ESP_SYSTEM_RTC_EXT_XTAL
default 5 if IDF_TARGET_ESP32
default 0
range 0 32768
help
To reduce the startup time of an external RTC crystal,
we bootstrap it with a 32kHz square wave for a fixed number of cycles.
Setting 0 will disable bootstrapping (if disabled, the crystal may take
longer to start up or fail to oscillate under some conditions).
If this value is too high, a faulty crystal may initially start and then fail.
If this value is too low, an otherwise good crystal may not start.
To accurately determine if the crystal has started,
set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
bool
default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE
default y if IDF_TARGET_ESP32S2
default y if IDF_TARGET_ESP32C3
default y if IDF_TARGET_ESP32S3
config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
bool "Enable RTC fast memory for dynamic allocations"
default y if IDF_TARGET_ESP32
default y if IDF_TARGET_ESP32S2
default y if IDF_TARGET_ESP32C3
default n if IDF_TARGET_ESP32S3 # TODO
depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
help
This config option allows to add RTC fast memory region to system heap with capability
similar to that of DRAM region but without DMA. This memory will be consumed first per
heap initialization order by early startup services and scheduler related code. Speed
wise RTC fast memory operates on APB clock and hence does not have much performance impact.
config ESP_SYSTEM_PD_FLASH
bool "PD flash at light sleep when there is no SPIRAM"
depends on !SPIRAM
default y
help
If enabled, chip will try to power down flash at light sleep, which costs more time when chip wakes up.
Only can be enabled if there is no SPIRAM configured.
config ESP_SYSTEM_PM_POWER_DOWN_CPU
bool "Power down CPU in light sleep"
depends on IDF_TARGET_ESP32C3
default y
help
If enabled, the CPU will be powered down in light sleep. Enabling this option will consume
1.68 KB of internal RAM and will reduce sleep current consumption by about 100 uA.
menu "Memory protection"
config ESP_SYSTEM_MEMPROT_FEATURE
bool "Enable memory protection"
depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S2
default "y"
help
If enabled, the permission control module watches all the memory access and fires the panic handler
if a permission violation is detected. This feature automatically splits
the SRAM memory into data and instruction segments and sets Read/Execute permissions
for the instruction part (below given splitting address) and Read/Write permissions
for the data part (above the splitting address). The memory protection is effective
on all access through the IRAM0 and DRAM0 buses.
config ESP_SYSTEM_MEMPROT_FEATURE_LOCK
depends on ESP_SYSTEM_MEMPROT_FEATURE
bool "Lock memory protection settings"
default "y"
help
Once locked, memory protection settings cannot be changed anymore.
The lock is reset only on the chip startup.
endmenu # Memory protection
endmenu # ESP System Settings