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https://github.com/espressif/esp-idf.git
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b24ac487cb
This allows RTC_SLOW_MEM to be powered down in deep sleep if no other variables are placed into RTC_SLOW_MEM.
497 lines
17 KiB
Plaintext
497 lines
17 KiB
Plaintext
menu "ESP32-specific config"
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choice ESP32_DEFAULT_CPU_FREQ_MHZ
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prompt "CPU frequency"
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default ESP32_DEFAULT_CPU_FREQ_240
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help
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CPU frequency to be set on application startup.
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config ESP32_DEFAULT_CPU_FREQ_80
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bool "80 MHz"
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config ESP32_DEFAULT_CPU_FREQ_160
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bool "160 MHz"
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config ESP32_DEFAULT_CPU_FREQ_240
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bool "240 MHz"
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endchoice
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config ESP32_DEFAULT_CPU_FREQ_MHZ
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int
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default 80 if ESP32_DEFAULT_CPU_FREQ_80
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default 160 if ESP32_DEFAULT_CPU_FREQ_160
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default 240 if ESP32_DEFAULT_CPU_FREQ_240
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config MEMMAP_SMP
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bool "Reserve memory for two cores"
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default "y"
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help
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The ESP32 contains two cores. If you plan to only use one, you can disable this item
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to save some memory. (ToDo: Make this automatically depend on unicore support)
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config MEMMAP_TRACEMEM
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bool "Use TRAX tracing feature"
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default "n"
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help
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The ESP32 contains a feature which allows you to trace the execution path the processor
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has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
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of memory that can't be used for general purposes anymore. Disable this if you do not know
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what this is.
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config MEMMAP_TRACEMEM_TWOBANKS
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bool "Reserve memory for tracing both pro as well as app cpu execution"
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default "n"
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depends on MEMMAP_TRACEMEM && MEMMAP_SMP
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help
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The ESP32 contains a feature which allows you to trace the execution path the processor
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has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
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of memory that can't be used for general purposes anymore. Disable this if you do not know
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what this is.
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# Memory to reverse for trace, used in linker script
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config TRACEMEM_RESERVE_DRAM
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hex
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default 0x8000 if MEMMAP_TRACEMEM && MEMMAP_TRACEMEM_TWOBANKS
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default 0x4000 if MEMMAP_TRACEMEM && !MEMMAP_TRACEMEM_TWOBANKS
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default 0x0
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# Not implemented and/or needs new silicon rev to work
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config MEMMAP_SPISRAM
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bool "Use external SPI SRAM chip as main memory"
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depends on ESP32_NEEDS_NEW_SILICON_REV
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default "n"
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help
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The ESP32 can control an external SPI SRAM chip, adding the memory it contains to the
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main memory map. Enable this if you have this hardware and want to use it in the same
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way as on-chip RAM.
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config SYSTEM_EVENT_QUEUE_SIZE
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int "System event queue size"
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default 32
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help
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Config system event queue size in different application.
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config SYSTEM_EVENT_TASK_STACK_SIZE
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int "Event loop task stack size"
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default 2048
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help
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Config system event task stack size in different application.
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config MAIN_TASK_STACK_SIZE
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int "Main task stack size"
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default 4096
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help
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Config system event task stack size in different application.
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config NEWLIB_STDOUT_ADDCR
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bool "Standard-out output adds carriage return before newline"
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default y
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help
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Most people are used to end their printf strings with a newline. If this
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is sent as is to the serial port, most terminal programs will only move the
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cursor one line down, not also move it to the beginning of the line. This
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is usually done by an added CR character. Enabling this will make the
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standard output code automatically add a CR character before a LF.
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config NEWLIB_NANO_FORMAT
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bool "Enable 'nano' formatting options for printf/scanf family"
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default n
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help
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ESP32 ROM contains parts of newlib C library, including printf/scanf family
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of functions. These functions have been compiled with so-called "nano"
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formatting option. This option doesn't support 64-bit integer formats and C99
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features, such as positional arguments.
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For more details about "nano" formatting option, please see newlib readme file,
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search for '--enable-newlib-nano-formatted-io':
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https://sourceware.org/newlib/README
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If this option is enabled, build system will use functions available in
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ROM, reducing the application binary size. Functions available in ROM run
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faster than functions which run from flash. Functions available in ROM can
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also run when flash instruction cache is disabled.
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If you need 64-bit integer formatting support or C99 features, keep this
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option disabled.
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choice CONSOLE_UART
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prompt "UART for console output"
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default CONSOLE_UART_DEFAULT
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help
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Select whether to use UART for console output (through stdout and stderr).
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- Default is to use UART0 on pins GPIO1(TX) and GPIO3(RX).
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- If "Custom" is selected, UART0 or UART1 can be chosen,
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and any pins can be selected.
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- If "None" is selected, there will be no console output on any UART, except
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for initial output from ROM bootloader. This output can be further suppressed by
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bootstrapping GPIO13 pin to low logic level.
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config CONSOLE_UART_DEFAULT
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bool "Default: UART0, TX=GPIO1, RX=GPIO3"
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config CONSOLE_UART_CUSTOM
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bool "Custom"
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config CONSOLE_UART_NONE
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bool "None"
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endchoice
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choice CONSOLE_UART_NUM
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prompt "UART peripheral to use for console output (0-1)"
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depends on CONSOLE_UART_CUSTOM
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default CONSOLE_UART_CUSTOM_NUM_0
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help
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Due of a ROM bug, UART2 is not supported for console output
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via ets_printf.
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config CONSOLE_UART_CUSTOM_NUM_0
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bool "UART0"
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config CONSOLE_UART_CUSTOM_NUM_1
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bool "UART1"
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endchoice
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config CONSOLE_UART_NUM
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int
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default 0 if CONSOLE_UART_DEFAULT || CONSOLE_UART_NONE
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default 0 if CONSOLE_UART_CUSTOM_NUM_0
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default 1 if CONSOLE_UART_CUSTOM_NUM_1
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config CONSOLE_UART_TX_GPIO
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int "UART TX on GPIO#"
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depends on CONSOLE_UART_CUSTOM
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range 0 33
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default 19
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config CONSOLE_UART_RX_GPIO
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int "UART RX on GPIO#"
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depends on CONSOLE_UART_CUSTOM
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range 0 39
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default 21
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config CONSOLE_UART_BAUDRATE
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int "UART console baud rate"
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depends on !CONSOLE_UART_NONE
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default 115200
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range 1200 4000000
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config ULP_COPROC_ENABLED
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bool "Enable Ultra Low Power (ULP) Coprocessor"
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default "n"
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help
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Set to 'y' if you plan to load a firmware for the coprocessor.
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If this option is enabled, further coprocessor configuration will appear in the Components menu.
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config ULP_COPROC_RESERVE_MEM
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int "RTC slow memory reserved for coprocessor"
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default 512
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range 32 8192
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depends on ULP_COPROC_ENABLED
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help
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Bytes of memory to reserve for ULP coprocessor firmware & data.
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Data is reserved at the beginning of RTC slow memory.
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# Set CONFIG_ULP_COPROC_RESERVE_MEM to 0 if ULP is disabled
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config ULP_COPROC_RESERVE_MEM
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int
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default 0
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depends on !ULP_COPROC_ENABLED
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choice ESP32_PANIC
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prompt "Panic handler behaviour"
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default ESP32_PANIC_PRINT_REBOOT
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help
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If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
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invoked. Configure the panic handlers action here.
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config ESP32_PANIC_PRINT_HALT
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bool "Print registers and halt"
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help
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Outputs the relevant registers over the serial port and halt the
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processor. Needs a manual reset to restart.
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config ESP32_PANIC_PRINT_REBOOT
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bool "Print registers and reboot"
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help
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Outputs the relevant registers over the serial port and immediately
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reset the processor.
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config ESP32_PANIC_SILENT_REBOOT
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bool "Silent reboot"
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help
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Just resets the processor without outputting anything
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config ESP32_PANIC_GDBSTUB
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bool "Invoke GDBStub"
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help
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Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
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of the crash.
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endchoice
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config ESP32_DEBUG_OCDAWARE
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bool "Make exception and panic handlers JTAG/OCD aware"
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default y
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help
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The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and
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instead of panicking, have the debugger stop on the offending instruction.
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config INT_WDT
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bool "Interrupt watchdog"
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default y
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help
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This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
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either because a task turned off interrupts and did not turn them on for a long time, or because an
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interrupt handler did not return. It will try to invoke the panic handler first and failing that
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reset the SoC.
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config INT_WDT_TIMEOUT_MS
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int "Interrupt watchdog timeout (ms)"
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depends on INT_WDT
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default 300
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range 10 10000
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help
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The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
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config INT_WDT_CHECK_CPU1
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bool "Also watch CPU1 tick interrupt"
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depends on INT_WDT && !FREERTOS_UNICORE
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default y
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help
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Also detect if interrupts on CPU 1 are disabled for too long.
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config TASK_WDT
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bool "Task watchdog"
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default y
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help
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This watchdog timer can be used to make sure individual tasks are still running.
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config TASK_WDT_PANIC
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bool "Invoke panic handler when Task Watchdog is triggered"
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depends on TASK_WDT
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default n
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help
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Normally, the Task Watchdog will only print out a warning if it detects it has not
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been fed. If this is enabled, it will invoke the panic handler instead, which
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can then halt or reboot the chip.
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config TASK_WDT_TIMEOUT_S
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int "Task watchdog timeout (seconds)"
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depends on TASK_WDT
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range 1 60
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default 5
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help
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Timeout for the task WDT, in seconds.
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config TASK_WDT_CHECK_IDLE_TASK
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bool "Task watchdog watches CPU0 idle task"
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depends on TASK_WDT
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default y
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help
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With this turned on, the task WDT can detect if the idle task is not called within the task
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watchdog timeout period. The idle task not being called usually is a symptom of another
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task hoarding the CPU. It is also a bad thing because FreeRTOS household tasks depend on the
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idle task getting some runtime every now and then. Take Care: With this disabled, this
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watchdog will trigger if no tasks register themselves within the timeout value.
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config TASK_WDT_CHECK_IDLE_TASK_CPU1
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bool "Task watchdog also watches CPU1 idle task"
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depends on TASK_WDT_CHECK_IDLE_TASK && !FREERTOS_UNICORE
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default y
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help
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Also check the idle task that runs on CPU1.
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#The brownout detector code is disabled (by making it depend on a nonexisting symbol) because the current revision of ESP32
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#silicon has a bug in the brown-out detector, rendering it unusable for resetting the CPU.
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config BROWNOUT_DET
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bool "Hardware brownout detect & reset"
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default y
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depends on NEEDS_ESP32_NEW_SILICON_REV
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help
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The ESP32 has a built-in brownout detector which can detect if the voltage is lower than
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a specific value. If this happens, it will reset the chip in order to prevent unintended
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behaviour.
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choice BROWNOUT_DET_LVL_SEL
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prompt "Brownout voltage level"
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depends on BROWNOUT_DET
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default BROWNOUT_DET_LVL_SEL_25
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help
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The brownout detector will reset the chip when the supply voltage is below this level.
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#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
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#of the brownout threshold levels.
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config BROWNOUT_DET_LVL_SEL_0
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bool "2.1V"
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config BROWNOUT_DET_LVL_SEL_1
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bool "2.2V"
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config BROWNOUT_DET_LVL_SEL_2
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bool "2.3V"
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config BROWNOUT_DET_LVL_SEL_3
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bool "2.4V"
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config BROWNOUT_DET_LVL_SEL_4
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bool "2.5V"
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config BROWNOUT_DET_LVL_SEL_5
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bool "2.6V"
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config BROWNOUT_DET_LVL_SEL_6
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bool "2.7V"
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config BROWNOUT_DET_LVL_SEL_7
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bool "2.8V"
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endchoice
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config BROWNOUT_DET_LVL
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int
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default 0 if BROWNOUT_DET_LVL_SEL_0
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default 1 if BROWNOUT_DET_LVL_SEL_1
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default 2 if BROWNOUT_DET_LVL_SEL_2
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default 3 if BROWNOUT_DET_LVL_SEL_3
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default 4 if BROWNOUT_DET_LVL_SEL_4
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default 5 if BROWNOUT_DET_LVL_SEL_5
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default 6 if BROWNOUT_DET_LVL_SEL_6
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default 7 if BROWNOUT_DET_LVL_SEL_7
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config BROWNOUT_DET_RESETDELAY
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int "Brownout reset delay (in uS)"
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depends on BROWNOUT_DET
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range 0 6820
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default 1000
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help
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The brownout detector can reset the chip after a certain delay, in order to make sure e.g. a voltage dip has entirely passed
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before trying to restart the chip. You can set the delay here.
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choice ESP32_TIME_SYSCALL
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prompt "Timers used for gettimeofday function"
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default ESP32_TIME_SYSCALL_USE_RTC_FRC1
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help
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This setting defines which hardware timers are used to
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implement 'gettimeofday' and 'time' functions in C library.
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- If only FRC1 timer is used, gettimeofday will provide time at
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microsecond resolution. Time will not be preserved when going
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into deep sleep mode.
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- If both FRC1 and RTC timers are used, timekeeping will
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continue in deep sleep. Time will be reported at 1 microsecond
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resolution.
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- If only RTC timer is used, timekeeping will continue in
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deep sleep, but time will be measured at 6.(6) microsecond
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resolution. Also the gettimeofday function itself may take
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longer to run.
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- If no timers are used, gettimeofday and time functions
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return -1 and set errno to ENOSYS.
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- When RTC is used for timekeeping, two RTC_STORE registers are
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used to keep time in deep sleep mode.
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config ESP32_TIME_SYSCALL_USE_RTC
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bool "RTC"
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config ESP32_TIME_SYSCALL_USE_RTC_FRC1
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bool "RTC and FRC1"
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config ESP32_TIME_SYSCALL_USE_FRC1
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bool "FRC1"
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config ESP32_TIME_SYSCALL_USE_NONE
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bool "None"
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endchoice
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choice ESP32_RTC_CLOCK_SOURCE
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prompt "RTC clock source"
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default ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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help
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Choose which clock is used as RTC clock source.
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The only available option for now is to use internal
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150kHz RC oscillator.
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config ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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bool "Internal RC"
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config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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bool "External 32kHz crystal"
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depends on DOCUMENTATION_FOR_RTC_CNTL
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endchoice
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config ESP32_DEEP_SLEEP_WAKEUP_DELAY
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int "Extra delay in deep sleep wake stub (in us)"
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default 0
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range 0 5000
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help
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When ESP32 exits deep sleep, the CPU and the flash chip are powered on
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at the same time. CPU will run deep sleep stub first, and then
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proceed to load code from flash. Some flash chips need sufficient
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time to pass between power on and first read operation. By default,
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without any extra delay, this time is approximately 900us.
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If you are using a flash chip which needs more than 900us to become
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ready after power on, set this parameter to add extra delay
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to the default deep sleep stub.
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If you are seeing "flash read err, 1000" message printed to the
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console after deep sleep reset, try increasing this value.
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endmenu
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menuconfig WIFI_ENABLED
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bool "WiFi"
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default y
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help
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Select this option to enable WiFi stack and show the submenu with WiFi configuration choices.
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config SW_COEXIST_ENABLE
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bool "Software controls WiFi/Bluetooth coexistence"
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depends on WIFI_ENABLED && BT_ENABLED
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default n
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help
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If enabled, WiFi & Bluetooth coexistence is controlled by software rather than hardware.
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Recommended for heavy traffic scenarios. Both coexistence configuration options are
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automatically managed, no user intervention is required.
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config ESP32_PHY_AUTO_INIT
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bool "Initialize PHY in startup code"
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depends on WIFI_ENABLED
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default y
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help
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If enabled, PHY will be initialized in startup code, before
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app_main function runs.
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If this is undesired, disable this option and call esp_phy_init
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from the application before enabling WiFi or BT.
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If this option is enabled, startup code will also initialize
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NVS prior to initializing PHY.
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If unsure, choose 'y'.
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config ESP32_PHY_INIT_DATA_IN_PARTITION
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bool "Use a partition to store PHY init data"
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depends on WIFI_ENABLED
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default n
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help
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If enabled, PHY init data will be loaded from a partition.
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When using a custom partition table, make sure that PHY data
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partition is included (type: 'data', subtype: 'phy').
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With default partition tables, this is done automatically.
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If PHY init data is stored in a partition, it has to be flashed there,
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otherwise runtime error will occur.
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If this option is not enabled, PHY init data will be embedded
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into the application binary.
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If unsure, choose 'n'.
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config ESP32_PHY_MAX_TX_POWER
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int "Max TX power (dBm)"
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range 0 20
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default 20
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depends on WIFI_ENABLED
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help
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Set maximum transmit power. Actual transmit power for high
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data rates may be lower than this setting.
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config ESP32_WIFI_RX_BUFFER_NUM
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int "Max number of WiFi RX buffers"
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depends on WIFI_ENABLED
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range 2 25
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default 25
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help
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Set the number of WiFi rx buffers. Each buffer takes approximately 1.6KB of RAM.
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Larger number for higher throughput but more memory. Smaller number for lower
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throughput but less memory.
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