mirror of
https://github.com/espressif/esp-idf.git
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307 lines
8.7 KiB
C
307 lines
8.7 KiB
C
/*
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* ESP hardware accelerated SHA1/256/512 implementation
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* based on mbedTLS FIPS-197 compliant version.
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*
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* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
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* Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE Ltd
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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/*
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* The SHA-1 standard was published by NIST in 1993.
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*
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* http://www.itl.nist.gov/fipspubs/fip180-1.htm
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*/
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#include <string.h>
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#include <stdio.h>
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#include <sys/lock.h>
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#include "esp_log.h"
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#include "esp_memory_utils.h"
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#include "esp_crypto_lock.h"
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#include "esp_attr.h"
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#include "soc/lldesc.h"
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#include "soc/ext_mem_defs.h"
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#include "soc/periph_defs.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "esp_private/periph_ctrl.h"
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#include "sys/param.h"
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#include "sha/sha_dma.h"
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#include "hal/sha_hal.h"
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#include "soc/soc_caps.h"
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#include "esp_sha_dma_priv.h"
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32s3/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/cache.h"
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#endif
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#if SOC_SHA_GDMA
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#define SHA_LOCK() esp_crypto_sha_aes_lock_acquire()
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#define SHA_RELEASE() esp_crypto_sha_aes_lock_release()
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#elif SOC_SHA_CRYPTO_DMA
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#define SHA_LOCK() esp_crypto_dma_lock_acquire()
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#define SHA_RELEASE() esp_crypto_dma_lock_release()
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#endif
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const static char *TAG = "esp-sha";
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static bool s_check_dma_capable(const void *p);
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/* These are static due to:
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* * Must be in DMA capable memory, so stack is not a safe place to put them
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* * To avoid having to malloc/free them for every DMA operation
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*/
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static DRAM_ATTR lldesc_t s_dma_descr_input;
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static DRAM_ATTR lldesc_t s_dma_descr_buf;
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void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state)
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{
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sha_hal_write_digest(sha_type, digest_state);
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}
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void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state)
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{
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sha_hal_read_digest(sha_type, digest_state);
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}
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/* Return block size (in bytes) for a given SHA type */
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inline static size_t block_length(esp_sha_type type)
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{
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switch (type) {
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case SHA1:
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case SHA2_224:
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case SHA2_256:
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return 64;
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#if SOC_SHA_SUPPORT_SHA384
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case SHA2_384:
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#endif
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#if SOC_SHA_SUPPORT_SHA512
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case SHA2_512:
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#endif
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#if SOC_SHA_SUPPORT_SHA512_T
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case SHA2_512224:
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case SHA2_512256:
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case SHA2_512T:
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#endif
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return 128;
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default:
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return 0;
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}
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}
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/* Enable SHA peripheral and then lock it */
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void esp_sha_acquire_hardware()
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{
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SHA_LOCK(); /* Released when releasing hw with esp_sha_release_hardware() */
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/* Enable SHA and DMA hardware */
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#if SOC_SHA_CRYPTO_DMA
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periph_module_enable(PERIPH_SHA_DMA_MODULE);
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#elif SOC_SHA_GDMA
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periph_module_enable(PERIPH_SHA_MODULE);
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#endif
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}
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/* Disable SHA peripheral block and then release it */
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void esp_sha_release_hardware()
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{
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/* Disable SHA and DMA hardware */
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#if SOC_SHA_CRYPTO_DMA
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periph_module_disable(PERIPH_SHA_DMA_MODULE);
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#elif SOC_SHA_GDMA
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periph_module_disable(PERIPH_SHA_MODULE);
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#endif
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SHA_RELEASE();
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}
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/* Hash the input block by block, using non-DMA mode */
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static void esp_sha_block_mode(esp_sha_type sha_type, const uint8_t *input, uint32_t ilen,
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const uint8_t *buf, uint32_t buf_len, bool is_first_block)
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{
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size_t blk_len = 0;
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size_t blk_word_len = 0;
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int num_block = 0;
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blk_len = block_length(sha_type);
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blk_word_len = blk_len / 4;
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num_block = ilen / blk_len;
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if (buf_len != 0) {
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sha_hal_hash_block(sha_type, buf, blk_word_len, is_first_block);
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is_first_block = false;
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}
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for (int i = 0; i < num_block; i++) {
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sha_hal_hash_block(sha_type, input + blk_len * i, blk_word_len, is_first_block);
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is_first_block = false;
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}
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}
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static int esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block);
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/* Performs SHA on multiple blocks at a time using DMA
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splits up into smaller operations for inputs that exceed a single DMA list
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*/
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int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block)
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{
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int ret = 0;
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unsigned char *dma_cap_buf = NULL;
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if (buf_len > block_length(sha_type)) {
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ESP_LOGE(TAG, "SHA DMA buf_len cannot exceed max size for a single block");
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return -1;
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}
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/* DMA cannot access memory in flash, hash block by block instead of using DMA */
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if (!s_check_dma_capable(input) && (ilen != 0)) {
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esp_sha_block_mode(sha_type, input, ilen, buf, buf_len, is_first_block);
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return 0;
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}
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#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
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if (esp_ptr_external_ram(input)) {
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Cache_WriteBack_Addr((uint32_t)input, ilen);
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}
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if (esp_ptr_external_ram(buf)) {
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Cache_WriteBack_Addr((uint32_t)buf, buf_len);
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}
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#endif
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/* Copy to internal buf if buf is in non DMA capable memory */
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if (!s_check_dma_capable(buf) && (buf_len != 0)) {
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dma_cap_buf = heap_caps_malloc(sizeof(unsigned char) * buf_len, MALLOC_CAP_8BIT|MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
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if (dma_cap_buf == NULL) {
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ESP_LOGE(TAG, "Failed to allocate buf memory");
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ret = -1;
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goto cleanup;
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}
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memcpy(dma_cap_buf, buf, buf_len);
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buf = dma_cap_buf;
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}
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uint32_t dma_op_num;
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if (ilen > 0) {
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/* Number of DMA operations based on maximum chunk size in single operation */
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dma_op_num = (ilen + SOC_SHA_DMA_MAX_BUFFER_SIZE - 1) / SOC_SHA_DMA_MAX_BUFFER_SIZE;
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} else {
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/* For zero input length, we must allow at-least 1 DMA operation to see
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* if there is any pending data that is yet to be copied out */
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dma_op_num = 1;
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}
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/* The max amount of blocks in a single hardware operation is 2^6 - 1 = 63
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Thus we only do a single DMA input list + dma buf list,
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which is max 3968/64 + 64/64 = 63 blocks */
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for (int i = 0; i < dma_op_num; i++) {
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int dma_chunk_len = MIN(ilen, SOC_SHA_DMA_MAX_BUFFER_SIZE);
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ret = esp_sha_dma_process(sha_type, input, dma_chunk_len, buf, buf_len, is_first_block);
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if (ret != 0) {
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goto cleanup;
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}
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ilen -= dma_chunk_len;
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input = (uint8_t *)input + dma_chunk_len;
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// Only append buf to the first operation
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buf_len = 0;
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is_first_block = false;
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}
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cleanup:
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free(dma_cap_buf);
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return ret;
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}
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/* Performs SHA on multiple blocks at a time */
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static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block)
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{
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int ret = 0;
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lldesc_t *dma_descr_head = NULL;
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size_t num_blks = (ilen + buf_len) / block_length(sha_type);
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memset(&s_dma_descr_input, 0, sizeof(lldesc_t));
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memset(&s_dma_descr_buf, 0, sizeof(lldesc_t));
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/* DMA descriptor for Memory to DMA-SHA transfer */
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if (ilen) {
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s_dma_descr_input.length = ilen;
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s_dma_descr_input.size = ilen;
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s_dma_descr_input.owner = 1;
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s_dma_descr_input.eof = 1;
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s_dma_descr_input.buf = (uint8_t *)input;
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dma_descr_head = &s_dma_descr_input;
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}
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/* Check after input to overide head if there is any buf*/
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if (buf_len) {
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s_dma_descr_buf.length = buf_len;
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s_dma_descr_buf.size = buf_len;
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s_dma_descr_buf.owner = 1;
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s_dma_descr_buf.eof = 1;
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s_dma_descr_buf.buf = (uint8_t *)buf;
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dma_descr_head = &s_dma_descr_buf;
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}
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/* Link DMA lists */
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if (buf_len && ilen) {
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s_dma_descr_buf.eof = 0;
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s_dma_descr_buf.empty = (uint32_t)(&s_dma_descr_input);
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}
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if (esp_sha_dma_start(dma_descr_head) != ESP_OK) {
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ESP_LOGE(TAG, "esp_sha_dma_start failed, no DMA channel available");
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return -1;
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}
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sha_hal_hash_dma(sha_type, num_blks, is_first_block);
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sha_hal_wait_idle();
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return ret;
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}
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static bool s_check_dma_capable(const void *p)
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{
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bool is_capable = false;
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#if CONFIG_SPIRAM
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is_capable |= esp_ptr_dma_ext_capable(p);
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#endif
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is_capable |= esp_ptr_dma_capable(p);
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return is_capable;
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}
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