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https://github.com/espressif/esp-idf.git
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e44df658d5
Requirement to enable for ESP32-S2 captured in IDF-912.
218 lines
8.2 KiB
C
218 lines
8.2 KiB
C
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/soc.h"
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#ifdef CONFIG_BT_ENABLED
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#define SOC_MEM_BT_DATA_START 0x3ffae6e0
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#define SOC_MEM_BT_DATA_END 0x3ffaff10
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#define SOC_MEM_BT_EM_START 0x3ffb0000
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#define SOC_MEM_BT_EM_END 0x3ffb7cd8
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#define SOC_MEM_BT_EM_BTDM0_START 0x3ffb0000
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#define SOC_MEM_BT_EM_BTDM0_END 0x3ffb09a8
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#define SOC_MEM_BT_EM_BLE_START 0x3ffb09a8
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#define SOC_MEM_BT_EM_BLE_END 0x3ffb1ddc
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#define SOC_MEM_BT_EM_BTDM1_START 0x3ffb1ddc
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#define SOC_MEM_BT_EM_BTDM1_END 0x3ffb2730
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#define SOC_MEM_BT_EM_BREDR_START 0x3ffb2730
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#define SOC_MEM_BT_EM_BREDR_NO_SYNC_END 0x3ffb6388 //Not calculate with synchronize connection support
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#define SOC_MEM_BT_EM_BREDR_END 0x3ffb7cd8 //Calculate with synchronize connection support
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#define SOC_MEM_BT_EM_SYNC0_START 0x3ffb6388
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#define SOC_MEM_BT_EM_SYNC0_END 0x3ffb6bf8
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#define SOC_MEM_BT_EM_SYNC1_START 0x3ffb6bf8
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#define SOC_MEM_BT_EM_SYNC1_END 0x3ffb7468
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#define SOC_MEM_BT_EM_SYNC2_START 0x3ffb7468
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#define SOC_MEM_BT_EM_SYNC2_END 0x3ffb7cd8
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#define SOC_MEM_BT_BSS_START 0x3ffb8000
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#define SOC_MEM_BT_BSS_END 0x3ffb9a20
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#define SOC_MEM_BT_MISC_START 0x3ffbdb28
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#define SOC_MEM_BT_MISC_END 0x3ffbdb5c
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#define SOC_MEM_BT_EM_PER_SYNC_SIZE 0x870
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#define SOC_MEM_BT_EM_BREDR_REAL_END (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE)
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#endif //CONFIG_BT_ENABLED
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#define SOC_MEMORY_TYPE_NO_PRIOS 3
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/* Type descriptor holds a description for a particular type of memory on a particular SoC.
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*/
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typedef struct {
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const char *name; ///< Name of this memory type
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uint32_t caps[SOC_MEMORY_TYPE_NO_PRIOS]; ///< Capabilities for this memory type (as a prioritised set)
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bool aliased_iram; ///< If true, this is data memory that is is also mapped in IRAM
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bool startup_stack; ///< If true, memory of this type is used for ROM stack during startup
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} soc_memory_type_desc_t;
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/* Constant table of tag descriptors for all this SoC's tags */
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extern const soc_memory_type_desc_t soc_memory_types[];
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extern const size_t soc_memory_type_count;
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/* Region descriptor holds a description for a particular region of memory on a particular SoC.
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*/
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typedef struct
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{
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intptr_t start; ///< Start address of the region
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size_t size; ///< Size of the region in bytes
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size_t type; ///< Type of the region (index into soc_memory_types array)
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intptr_t iram_address; ///< If non-zero, is equivalent address in IRAM
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} soc_memory_region_t;
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extern const soc_memory_region_t soc_memory_regions[];
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extern const size_t soc_memory_region_count;
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/* Region descriptor holds a description for a particular region of
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memory reserved on this SoC for a particular use (ie not available
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for stack/heap usage.) */
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typedef struct
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{
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intptr_t start;
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intptr_t end;
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} soc_reserved_region_t;
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/* Use this macro to reserved a fixed region of RAM (hardcoded addresses)
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* for a particular purpose.
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*
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* Usually used to mark out memory addresses needed for hardware or ROM code
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* purposes.
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*
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* Don't call this macro from user code which can use normal C static allocation
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* instead.
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*
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* @param START Start address to be reserved.
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* @param END One after the address of the last byte to be reserved. (ie length of
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* the reserved region is (END - START) in bytes.
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* @param NAME Name for the reserved region. Must be a valid variable name,
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* unique to this source file.
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*/
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#define SOC_RESERVE_MEMORY_REGION(START, END, NAME) \
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__attribute__((section(".reserved_memory_address"))) __attribute__((used)) \
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static soc_reserved_region_t reserved_region_##NAME = { START, END };
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/* Return available memory regions for this SoC. Each available memory
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* region is a contiguous piece of memory which is not being used by
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* static data, used by ROM code, or reserved by a component using
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* the SOC_RESERVE_MEMORY_REGION() macro.
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*
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* This result is soc_memory_regions[] minus all regions reserved
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* via the SOC_RESERVE_MEMORY_REGION() macro (which may also split
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* some regions up.)
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*
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* At startup, all available memory returned by this function is
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* registered as heap space.
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*
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* @note OS-level startup function only, not recommended to call from
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* app code.
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*
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* @param regions Pointer to an array for reading available regions into.
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* Size of the array should be at least the result of
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* soc_get_available_memory_region_max_count(). Entries in the array
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* will be ordered by memory address.
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*
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* @return Number of entries copied to 'regions'. Will be no greater than
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* the result of soc_get_available_memory_region_max_count().
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*/
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size_t soc_get_available_memory_regions(soc_memory_region_t *regions);
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/* Return the maximum number of available memory regions which could be
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* returned by soc_get_available_memory_regions(). Used to size the
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* array passed to that function.
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*/
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size_t soc_get_available_memory_region_max_count(void);
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inline static bool IRAM_ATTR esp_ptr_dma_capable(const void *p)
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{
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return (intptr_t)p >= SOC_DMA_LOW && (intptr_t)p < SOC_DMA_HIGH;
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}
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inline static bool IRAM_ATTR esp_ptr_word_aligned(const void *p)
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{
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return ((intptr_t)p) % 4 == 0;
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}
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inline static bool IRAM_ATTR esp_ptr_executable(const void *p)
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{
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intptr_t ip = (intptr_t) p;
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return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
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|| (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
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|| (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
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}
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inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
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{
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intptr_t ip = (intptr_t) p;
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bool r;
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r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
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#if CONFIG_SPIRAM
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#if CONFIG_SPIRAM_SIZE != -1 // Fixed size, can be more accurate
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r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE));
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#else
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r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_HIGH));
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#endif
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#endif
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return r;
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}
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inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
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bool r;
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r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
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r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
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return r;
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}
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inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
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return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
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}
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inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) {
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#if !CONFIG_FREERTOS_UNICORE || CONFIG_IDF_TARGET_ESP32S2BETA
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return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
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#else
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return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
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#endif
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}
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inline static bool IRAM_ATTR esp_ptr_in_drom(const void *p) {
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return ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < SOC_DROM_HIGH);
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}
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inline static bool IRAM_ATTR esp_ptr_in_dram(const void *p) {
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return ((intptr_t)p >= SOC_DRAM_LOW && (intptr_t)p < SOC_DRAM_HIGH);
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}
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inline static bool IRAM_ATTR esp_ptr_in_diram_dram(const void *p) {
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return ((intptr_t)p >= SOC_DIRAM_DRAM_LOW && (intptr_t)p < SOC_DIRAM_DRAM_HIGH);
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}
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inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) {
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return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
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}
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inline static bool IRAM_ATTR esp_stack_ptr_is_sane(uint32_t sp)
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{
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//Check if stack ptr is in between SOC_DRAM_LOW and SOC_DRAM_HIGH, and 16 byte aligned.
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return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0));
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}
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