mirror of
https://github.com/espressif/esp-idf.git
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138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//replacement for gcc built-in functions
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#include "sdkconfig.h"
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#include <stdbool.h>
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#include "xtensa/config/core-isa.h"
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#include "xtensa/xtruntime.h"
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//reserved to measure atomic operation time
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#define atomic_benchmark_intr_disable()
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#define atomic_benchmark_intr_restore(STATE)
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// This allows nested interrupts disabling and restoring via local registers or stack.
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// They can be called from interrupts too.
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// WARNING: Only applies to current CPU.
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#define _ATOMIC_ENTER_CRITICAL(void) ({ \
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unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); \
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atomic_benchmark_intr_disable(); \
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state; \
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})
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#define _ATOMIC_EXIT_CRITICAL(state) do { \
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atomic_benchmark_intr_restore(state); \
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XTOS_RESTORE_JUST_INTLEVEL(state); \
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} while (0)
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#define CMP_EXCHANGE(n, type) bool __atomic_compare_exchange_ ## n (type* mem, type* expect, type desired, int success, int failure) \
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{ \
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bool ret = false; \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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if (*mem == *expect) { \
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ret = true; \
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*mem = desired; \
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} else { \
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*expect = *mem; \
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} \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_ADD(n, type) type __atomic_fetch_add_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr + value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_SUB(n, type) type __atomic_fetch_sub_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr - value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_AND(n, type) type __atomic_fetch_and_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr & value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_OR(n, type) type __atomic_fetch_or_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr | value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_XOR(n, type) type __atomic_fetch_xor_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr ^ value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#ifndef XCHAL_HAVE_S32C1I
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#error "XCHAL_HAVE_S32C1I not defined, include correct header!"
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#endif
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//this piece of code should only be compiled if the cpu doesn't support atomic compare and swap (s32c1i)
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#if XCHAL_HAVE_S32C1I == 0
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#pragma GCC diagnostic ignored "-Wbuiltin-declaration-mismatch"
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CMP_EXCHANGE(1, uint8_t)
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CMP_EXCHANGE(2, uint16_t)
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CMP_EXCHANGE(4, uint32_t)
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CMP_EXCHANGE(8, uint64_t)
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FETCH_ADD(1, uint8_t)
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FETCH_ADD(2, uint16_t)
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FETCH_ADD(4, uint32_t)
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FETCH_ADD(8, uint64_t)
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FETCH_SUB(1, uint8_t)
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FETCH_SUB(2, uint16_t)
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FETCH_SUB(4, uint32_t)
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FETCH_SUB(8, uint64_t)
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FETCH_AND(1, uint8_t)
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FETCH_AND(2, uint16_t)
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FETCH_AND(4, uint32_t)
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FETCH_AND(8, uint64_t)
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FETCH_OR(1, uint8_t)
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FETCH_OR(2, uint16_t)
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FETCH_OR(4, uint32_t)
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FETCH_OR(8, uint64_t)
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FETCH_XOR(1, uint8_t)
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FETCH_XOR(2, uint16_t)
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FETCH_XOR(4, uint32_t)
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FETCH_XOR(8, uint64_t)
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#endif |