mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
874a720286
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
357 lines
15 KiB
C
357 lines
15 KiB
C
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_RTC_IO_STRUCT_H_
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#define _SOC_RTC_IO_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct rtc_io_dev_s {
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t data : 22; /*RTC GPIO 0 ~ 21 output data*/
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};
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uint32_t val;
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} out;
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 output data write 1 to set*/
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};
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uint32_t val;
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} out_w1ts;
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 output data write 1 to clear*/
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};
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uint32_t val;
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} out_w1tc;
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t enable : 22; /*RTC GPIO 0 ~ 21 enable*/
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};
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uint32_t val;
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} enable;
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 enable write 1 to set*/
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};
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uint32_t val;
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} enable_w1ts;
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 enable write 1 to clear*/
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};
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uint32_t val;
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} enable_w1tc;
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t status : 22; /*RTC GPIO 0 ~ 21 interrupt status*/
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};
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uint32_t val;
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} status;
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
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};
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uint32_t val;
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} status_w1ts;
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
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};
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uint32_t val;
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} status_w1tc;
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union {
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struct {
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uint32_t reserved0 : 10;
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uint32_t in : 22; /*RTC GPIO input data*/
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};
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uint32_t val;
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} in_val;
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union {
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struct {
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uint32_t reserved0 : 2;
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uint32_t pad_driver : 1; /*if set to 0: normal output, if set to 1: open drain*/
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uint32_t reserved3 : 4;
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uint32_t int_type : 3; /*if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger*/
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uint32_t wakeup_enable : 1; /*RTC GPIO wakeup enable bit*/
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uint32_t reserved11 : 21;
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};
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uint32_t val;
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} pin[22];
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union {
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struct {
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uint32_t sel0 : 5;
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uint32_t sel1 : 5;
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uint32_t sel2 : 5;
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uint32_t sel3 : 5;
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uint32_t sel4 : 5;
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uint32_t no_gating_12m : 1;
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uint32_t reserved26 : 6;
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};
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uint32_t val;
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} debug_sel;
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union {
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struct {
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uint32_t reserved0 : 13;
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uint32_t fun_ie : 1; /*input enable in work mode*/
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uint32_t slp_oe : 1; /*output enable in sleep mode*/
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uint32_t slp_ie : 1; /*input enable in sleep mode*/
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uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
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uint32_t fun_sel : 2; /*function sel*/
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uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
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uint32_t xpd : 1; /*TOUCH_XPD*/
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uint32_t tie_opt : 1; /*TOUCH_TIE_OPT*/
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uint32_t start : 1; /*TOUCH_START*/
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uint32_t reserved23 : 4;
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uint32_t rue : 1; /*RUE*/
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uint32_t rde : 1; /*RDE*/
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uint32_t drv : 2; /*DRV*/
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} touch_pad[15];
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union {
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struct {
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uint32_t reserved0 : 13;
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uint32_t x32p_fun_ie : 1; /*input enable in work mode*/
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uint32_t x32p_slp_oe : 1; /*output enable in sleep mode*/
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uint32_t x32p_slp_ie : 1; /*input enable in sleep mode*/
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uint32_t x32p_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
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uint32_t x32p_fun_sel : 2; /*function sel*/
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uint32_t x32p_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
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uint32_t reserved20 : 7;
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uint32_t x32p_rue : 1; /*RUE*/
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uint32_t x32p_rde : 1; /*RDE*/
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uint32_t x32p_drv : 2; /*DRV*/
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} xtal_32p_pad;
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union {
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struct {
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uint32_t reserved0 : 13;
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uint32_t x32n_fun_ie : 1; /*input enable in work mode*/
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uint32_t x32n_slp_oe : 1; /*output enable in sleep mode*/
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uint32_t x32n_slp_ie : 1; /*input enable in sleep mode*/
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uint32_t x32n_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
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uint32_t x32n_fun_sel : 2; /*function sel*/
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uint32_t x32n_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
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uint32_t reserved20 : 7;
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uint32_t x32n_rue : 1; /*RUE*/
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uint32_t x32n_rde : 1; /*RDE*/
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uint32_t x32n_drv : 2; /*DRV*/
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} xtal_32n_pad;
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union {
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struct {
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uint32_t reserved0 : 3;
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uint32_t dac : 8; /*PDAC1_DAC*/
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uint32_t xpd_dac : 1; /*PDAC1_XPD_DAC*/
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uint32_t dac_xpd_force : 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC*/
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uint32_t fun_ie : 1; /*input enable in work mode*/
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uint32_t slp_oe : 1; /*output enable in sleep mode*/
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uint32_t slp_ie : 1; /*input enable in sleep mode*/
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uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
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uint32_t fun_sel : 2; /*PDAC1 function sel*/
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uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
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uint32_t reserved20 : 7;
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uint32_t rue : 1; /*PDAC1_RUE*/
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uint32_t rde : 1; /*PDAC1_RDE*/
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uint32_t drv : 2; /*PDAC1_DRV*/
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} pad_dac[2];
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union {
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struct {
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uint32_t reserved0 : 13;
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uint32_t rtc_pad19_fun_ie : 1; /*input enable in work mode*/
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uint32_t rtc_pad19_slp_oe : 1; /*output enable in sleep mode*/
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uint32_t rtc_pad19_slp_ie : 1; /*input enable in sleep mode*/
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uint32_t rtc_pad19_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
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uint32_t rtc_pad19_fun_sel : 2; /*function sel*/
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uint32_t rtc_pad19_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
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uint32_t reserved20 : 7;
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uint32_t rtc_pad19_rue : 1; /*RUE*/
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uint32_t rtc_pad19_rde : 1; /*RDE*/
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uint32_t rtc_pad19_drv : 2; /*DRV*/
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} rtc_pad19;
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union {
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struct {
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uint32_t reserved0 : 13;
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uint32_t rtc_pad20_fun_ie : 1; /*input enable in work mode*/
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uint32_t rtc_pad20_slp_oe : 1; /*output enable in sleep mode*/
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uint32_t rtc_pad20_slp_ie : 1; /*input enable in sleep mode*/
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uint32_t rtc_pad20_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
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uint32_t rtc_pad20_fun_sel : 2; /*function sel*/
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uint32_t rtc_pad20_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
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uint32_t reserved20 : 7;
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uint32_t rtc_pad20_rue : 1; /*RUE*/
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uint32_t rtc_pad20_rde : 1; /*RDE*/
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uint32_t rtc_pad20_drv : 2; /*DRV*/
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} rtc_pad20;
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union {
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struct {
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uint32_t reserved0 : 13;
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uint32_t rtc_pad21_fun_ie : 1; /*input enable in work mode*/
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uint32_t rtc_pad21_slp_oe : 1; /*output enable in sleep mode*/
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uint32_t rtc_pad21_slp_ie : 1; /*input enable in sleep mode*/
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uint32_t rtc_pad21_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
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uint32_t rtc_pad21_fun_sel : 2; /*function sel*/
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uint32_t rtc_pad21_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
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uint32_t reserved20 : 7;
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uint32_t rtc_pad21_rue : 1; /*RUE*/
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uint32_t rtc_pad21_rde : 1; /*RDE*/
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uint32_t rtc_pad21_drv : 2; /*DRV*/
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} rtc_pad21;
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union {
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struct {
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uint32_t reserved0 : 27;
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uint32_t sel : 5;
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};
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uint32_t val;
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} ext_wakeup0;
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union {
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struct {
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uint32_t reserved0 : 27;
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uint32_t sel : 5; /*select RTC GPIO 0 ~ 17 to control XTAL*/
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};
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uint32_t val;
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} xtl_ext_ctr;
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union {
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struct {
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uint32_t reserved0 : 23;
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uint32_t debug_bit_sel : 5;
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uint32_t scl_sel : 2;
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uint32_t sda_sel : 2;
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};
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uint32_t val;
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} sar_i2c_io;
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union {
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struct {
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uint32_t io_touch_bufsel : 4; /*BUF_SEL when touch work without fsm*/
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uint32_t io_touch_bufmode : 1; /*BUF_MODE when touch work without fsm*/
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uint32_t reserved5 : 27;
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};
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uint32_t val;
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} touch_ctrl;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t reserved_fc;
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uint32_t reserved_100;
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uint32_t reserved_104;
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uint32_t reserved_108;
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uint32_t reserved_10c;
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uint32_t reserved_110;
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uint32_t reserved_114;
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uint32_t reserved_118;
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uint32_t reserved_11c;
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uint32_t reserved_120;
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uint32_t reserved_124;
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uint32_t reserved_128;
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uint32_t reserved_12c;
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uint32_t reserved_130;
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uint32_t reserved_134;
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uint32_t reserved_138;
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uint32_t reserved_13c;
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uint32_t reserved_140;
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uint32_t reserved_144;
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uint32_t reserved_148;
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uint32_t reserved_14c;
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uint32_t reserved_150;
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uint32_t reserved_154;
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uint32_t reserved_158;
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uint32_t reserved_15c;
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uint32_t reserved_160;
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uint32_t reserved_164;
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uint32_t reserved_168;
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uint32_t reserved_16c;
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uint32_t reserved_170;
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uint32_t reserved_174;
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uint32_t reserved_178;
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uint32_t reserved_17c;
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uint32_t reserved_180;
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uint32_t reserved_184;
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uint32_t reserved_188;
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uint32_t reserved_18c;
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uint32_t reserved_190;
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uint32_t reserved_194;
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uint32_t reserved_198;
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uint32_t reserved_19c;
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uint32_t reserved_1a0;
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uint32_t reserved_1a4;
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uint32_t reserved_1a8;
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uint32_t reserved_1ac;
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uint32_t reserved_1b0;
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uint32_t reserved_1b4;
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uint32_t reserved_1b8;
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uint32_t reserved_1bc;
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uint32_t reserved_1c0;
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uint32_t reserved_1c4;
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uint32_t reserved_1c8;
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uint32_t reserved_1cc;
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uint32_t reserved_1d0;
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uint32_t reserved_1d4;
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uint32_t reserved_1d8;
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uint32_t reserved_1dc;
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uint32_t reserved_1e0;
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uint32_t reserved_1e4;
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uint32_t reserved_1e8;
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uint32_t reserved_1ec;
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uint32_t reserved_1f0;
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uint32_t reserved_1f4;
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uint32_t reserved_1f8;
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union {
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struct {
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uint32_t date : 28;
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uint32_t reserved28 : 4;
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};
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uint32_t val;
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} date;
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} rtc_io_dev_t;
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extern rtc_io_dev_t RTCIO;
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#ifdef __cplusplus
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}
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#endif
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#endif /*_SOC_RTC_IO_STRUCT_H_ */
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