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https://github.com/espressif/esp-idf.git
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f7df532ec0
1. External 32kHz crystal is started for too long or it may not start at all. It is often observed at the first start. 2. At the first start, it is possible that the crystal did not start. And the recorded period was recorded as 0. Which led to a division error by zero during the transition to the deep sleep mode (Maybe somewhere else). 3. Added a unit test to test a new method of oscillation an external crystal. 4. Added a new method of oscillating of an external crystal. The legs of the crystal are fed with a 32 kHz frequency. The new method eliminates these errors. Added unit test: `\esp-idf\components\soc\esp32\test\test_rtc_clk.c`: `make TEST_COMPONENTS=soc` - 8 Test starting external RTC crystal. Will pass. `Bootstrap cycles for external 32kHz crystal` - is specified in the file Kconfig by default 100. QA tested a new method of oscillation the crystal on 25 boards. The supply of square waves on the crystal showed a 100% result in contrast to the previous method of launching the crystal. After the tests, the old method was deleted. Closes TW19143
283 lines
10 KiB
C
283 lines
10 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <sys/cdefs.h>
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#include <sys/time.h>
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_clk.h"
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#include "esp_clk_internal.h"
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#include "rom/ets_sys.h"
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#include "rom/uart.h"
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#include "rom/rtc.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/i2s_reg.h"
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#include "driver/periph_ctrl.h"
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#include "xtensa/core-macros.h"
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#include "bootloader_clock.h"
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/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
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* Larger values increase startup delay. Smaller values may cause false positive
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* detection (i.e. oscillator runs for a few cycles and then stops).
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*/
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#define XTAL_32K_DETECT_CYCLES 32
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#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32_RTC_CLK_CAL_CYCLES
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#define MHZ (1000000)
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static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk);
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// g_ticks_us defined in ROMs for PRO and APP CPU
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extern uint32_t g_ticks_per_us_pro;
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extern uint32_t g_ticks_per_us_app;
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static const char* TAG = "clk";
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void esp_clk_init(void)
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{
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rtc_config_t cfg = RTC_CONFIG_DEFAULT();
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rtc_init(cfg);
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#ifdef CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS
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/* Check the bootloader set the XTAL frequency.
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Bootloaders pre-v2.1 don't do this.
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*/
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rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
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ESP_EARLY_LOGW(TAG, "RTC domain not initialised by bootloader");
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bootloader_clock_configure();
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}
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#else
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/* If this assertion fails, either upgrade the bootloader or enable CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
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assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
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#endif
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rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
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#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
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#else
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select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
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#endif
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uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
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rtc_cpu_freq_t freq = RTC_CPU_FREQ_80M;
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switch(freq_mhz) {
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case 240:
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freq = RTC_CPU_FREQ_240M;
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break;
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case 160:
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freq = RTC_CPU_FREQ_160M;
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break;
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default:
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freq_mhz = 80;
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/* no break */
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case 80:
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freq = RTC_CPU_FREQ_80M;
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break;
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}
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// Wait for UART TX to finish, otherwise some UART output will be lost
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// when switching APB frequency
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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uint32_t freq_before = rtc_clk_cpu_freq_value(rtc_clk_cpu_freq_get()) / MHZ ;
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rtc_clk_cpu_freq_set(freq);
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// Re calculate the ccount to make time calculation correct.
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uint32_t freq_after = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
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XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before );
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}
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int IRAM_ATTR esp_clk_cpu_freq(void)
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{
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return g_ticks_per_us_pro * 1000000;
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}
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int IRAM_ATTR esp_clk_apb_freq(void)
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{
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return MIN(g_ticks_per_us_pro, 80) * 1000000;
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}
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void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
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{
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/* Update scale factors used by ets_delay_us */
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g_ticks_per_us_pro = ticks_per_us;
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g_ticks_per_us_app = ticks_per_us;
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}
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static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk)
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{
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uint32_t cal_val = 0;
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do {
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if (slow_clk == RTC_SLOW_FREQ_32K_XTAL) {
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/* 32k XTAL oscillator needs to be enabled and running before it can
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* be used. Hardware doesn't have a direct way of checking if the
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* oscillator is running. Here we use rtc_clk_cal function to count
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* the number of main XTAL cycles in the given number of 32k XTAL
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* oscillator cycles. If the 32k XTAL has not started up, calibration
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* will time out, returning 0.
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*/
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uint32_t wait = 0;
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// increment of 'wait' counter equivalent to 3 seconds
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const uint32_t warning_timeout = 3 /* sec */ * 32768 /* Hz */ / (2 * XTAL_32K_DETECT_CYCLES);
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ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up")
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do {
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++wait;
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rtc_clk_32k_enable(true);
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cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, XTAL_32K_DETECT_CYCLES);
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if (wait % warning_timeout == 0) {
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ESP_EARLY_LOGW(TAG, "still waiting for 32k oscillator to start up");
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}
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if(cal_val == 0){
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rtc_clk_32k_enable(false);
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rtc_clk_32k_bootstrap(CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES);
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}
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} while (cal_val == 0);
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}
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rtc_clk_slow_freq_set(slow_clk);
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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*/
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cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
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} else {
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const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
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}
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} while (cal_val == 0);
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ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
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esp_clk_slowclk_cal_set(cal_val);
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}
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void rtc_clk_select_rtc_slow_clk()
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{
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select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
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}
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/* This function is not exposed as an API at this point.
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* All peripheral clocks are default enabled after chip is powered on.
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* This function disables some peripheral clocks when cpu starts.
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* These peripheral clocks are enabled when the peripherals are initialized
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* and disabled when they are de-initialized.
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*/
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void esp_perip_clk_init(void)
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{
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uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
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#if CONFIG_FREERTOS_UNICORE
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RESET_REASON rst_reas[1];
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#else
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RESET_REASON rst_reas[2];
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#endif
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rst_reas[0] = rtc_get_reset_reason(0);
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#if !CONFIG_FREERTOS_UNICORE
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rst_reas[1] = rtc_get_reset_reason(1);
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#endif
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/* For reason that only reset CPU, do not disable the clocks
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* that have been enabled before reset.
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*/
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if ((rst_reas[0] >= TGWDT_CPU_RESET && rst_reas[0] <= RTCWDT_CPU_RESET)
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#if !CONFIG_FREERTOS_UNICORE
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|| (rst_reas[1] >= TGWDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
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#endif
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) {
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common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
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hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
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wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
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}
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else {
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common_perip_clk = DPORT_WDG_CLK_EN |
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DPORT_I2S0_CLK_EN |
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#if CONFIG_CONSOLE_UART_NUM != 0
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DPORT_UART_CLK_EN |
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#endif
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#if CONFIG_CONSOLE_UART_NUM != 1
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DPORT_UART1_CLK_EN |
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#endif
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#if CONFIG_CONSOLE_UART_NUM != 2
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DPORT_UART2_CLK_EN |
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#endif
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DPORT_SPI_CLK_EN |
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DPORT_I2C_EXT0_CLK_EN |
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DPORT_UHCI0_CLK_EN |
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DPORT_RMT_CLK_EN |
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DPORT_PCNT_CLK_EN |
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DPORT_LEDC_CLK_EN |
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DPORT_UHCI1_CLK_EN |
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DPORT_TIMERGROUP1_CLK_EN |
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DPORT_SPI_CLK_EN_2 |
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DPORT_PWM0_CLK_EN |
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DPORT_I2C_EXT1_CLK_EN |
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DPORT_CAN_CLK_EN |
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DPORT_PWM1_CLK_EN |
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DPORT_I2S1_CLK_EN |
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DPORT_SPI_DMA_CLK_EN |
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DPORT_PWM2_CLK_EN |
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DPORT_PWM3_CLK_EN;
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hwcrypto_perip_clk = DPORT_PERI_EN_AES |
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DPORT_PERI_EN_SHA |
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DPORT_PERI_EN_RSA |
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DPORT_PERI_EN_SECUREBOOT;
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wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
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DPORT_WIFI_CLK_BT_EN_M |
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DPORT_WIFI_CLK_UNUSED_BIT5 |
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DPORT_WIFI_CLK_UNUSED_BIT12 |
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DPORT_WIFI_CLK_SDIOSLAVE_EN |
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DPORT_WIFI_CLK_SDIO_HOST_EN |
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DPORT_WIFI_CLK_EMAC_EN;
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}
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#if CONFIG_SPIRAM_SPEED_80M
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//80MHz SPIRAM uses SPI2 as well; it's initialized before this is called. Because it is used in
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//a weird mode where clock to the peripheral is disabled but reset is also disabled, it 'hangs'
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//in a state where it outputs a continuous 80MHz signal. Mask its bit here because we should
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//not modify that state, regardless of what we calculated earlier.
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common_perip_clk &= ~DPORT_SPI_CLK_EN_2;
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#endif
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/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
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* the current is not reduced when disable I2S clock.
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*/
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DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(0), I2S_CLKA_ENA);
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DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(1), I2S_CLKA_ENA);
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/* Disable some peripheral clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
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/* Disable hardware crypto clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk);
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/* Disable WiFi/BT/SDIO clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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}
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