mirror of
https://github.com/espressif/esp-idf.git
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186 lines
6.8 KiB
C
186 lines
6.8 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** ECC_MULT_INT_RAW_REG register
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* ECC interrupt raw register, valid in level.
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*/
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#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
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/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the ecc_calc_done_int interrupt
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*/
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#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
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#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
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#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
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#define ECC_MULT_CALC_DONE_INT_RAW_S 0
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/** ECC_MULT_INT_ST_REG register
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* ECC interrupt status register.
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*/
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#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
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/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the ecc_calc_done_int interrupt
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*/
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#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
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#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
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#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
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#define ECC_MULT_CALC_DONE_INT_ST_S 0
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/** ECC_MULT_INT_ENA_REG register
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* ECC interrupt enable register.
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*/
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#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
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/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the ecc_calc_done_int interrupt
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*/
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#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
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#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
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#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
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#define ECC_MULT_CALC_DONE_INT_ENA_S 0
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/** ECC_MULT_INT_CLR_REG register
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* ECC interrupt clear register.
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*/
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#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
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/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the ecc_calc_done_int interrupt
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*/
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#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
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#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
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#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
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#define ECC_MULT_CALC_DONE_INT_CLR_S 0
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/** ECC_MULT_CONF_REG register
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* ECC configure register
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*/
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#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
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/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
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* Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
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* the caculatrion is done.
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*/
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#define ECC_MULT_START (BIT(0))
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#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
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#define ECC_MULT_START_V 0x00000001U
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#define ECC_MULT_START_S 0
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/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
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* Write 1 to reset ECC Accelerator.
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*/
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#define ECC_MULT_RESET (BIT(1))
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#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
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#define ECC_MULT_RESET_V 0x00000001U
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#define ECC_MULT_RESET_S 1
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/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
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* The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
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*/
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#define ECC_MULT_KEY_LENGTH (BIT(2))
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#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
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#define ECC_MULT_KEY_LENGTH_V 0x00000001U
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#define ECC_MULT_KEY_LENGTH_S 2
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/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
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* The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
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* 1: p(mod base of curve)
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*/
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#define ECC_MULT_MOD_BASE (BIT(3))
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#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
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#define ECC_MULT_MOD_BASE_V 0x00000001U
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#define ECC_MULT_MOD_BASE_S 3
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/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
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* The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
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* verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
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* Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
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* 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
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*/
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#define ECC_MULT_WORK_MODE 0x0000000FU
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#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
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#define ECC_MULT_WORK_MODE_V 0x0000000FU
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#define ECC_MULT_WORK_MODE_S 4
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/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
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* Reserved
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*/
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#define ECC_MULT_SECURITY_MODE (BIT(8))
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#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
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#define ECC_MULT_SECURITY_MODE_V 0x00000001U
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#define ECC_MULT_SECURITY_MODE_S 8
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/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
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* The verification result bit of ECC Accelerator, only valid when calculation is done.
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*/
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#define ECC_MULT_VERIFICATION_RESULT (BIT(29))
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#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
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#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
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#define ECC_MULT_VERIFICATION_RESULT_S 29
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/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
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* Write 1 to force on register clock gate.
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*/
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#define ECC_MULT_CLK_EN (BIT(30))
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#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
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#define ECC_MULT_CLK_EN_V 0x00000001U
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#define ECC_MULT_CLK_EN_S 30
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/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
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* ECC memory clock gate force on register
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*/
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#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
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#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
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#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
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#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
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/** ECC_MULT_DATE_REG register
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* Version control register
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*/
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#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
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/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 36720704;
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* ECC mult version control register
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*/
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#define ECC_MULT_DATE 0x0FFFFFFFU
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#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
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#define ECC_MULT_DATE_V 0x0FFFFFFFU
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#define ECC_MULT_DATE_S 0
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/** ECC_MULT_K_MEM register
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* The memory that stores k.
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*/
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#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
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#define ECC_MULT_K_MEM_SIZE_BYTES 32
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/** ECC_MULT_PX_MEM register
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* The memory that stores Px.
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*/
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#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
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#define ECC_MULT_PX_MEM_SIZE_BYTES 32
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/** ECC_MULT_PY_MEM register
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* The memory that stores Py.
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*/
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#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
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#define ECC_MULT_PY_MEM_SIZE_BYTES 32
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/** ECC_MULT_QX_MEM register
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* The memory that stores Qx.
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*/
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#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160)
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#define ECC_MULT_QX_MEM_SIZE_BYTES 32
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/** ECC_MULT_QY_MEM register
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* The memory that stores Qy.
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*/
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#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180)
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#define ECC_MULT_QY_MEM_SIZE_BYTES 32
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/** ECC_MULT_QZ_MEM register
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* The memory that stores Qz.
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*/
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#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1A0)
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#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
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#ifdef __cplusplus
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}
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#endif
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