mirror of
https://github.com/espressif/esp-idf.git
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150 lines
5.5 KiB
Plaintext
150 lines
5.5 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* ESP32-C6 Linker Script Memory Layout
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* This file describes the memory layout (memory blocks) by virtual memory addresses.
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* This linker script is passed through the C preprocessor to include configuration options.
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* Please use preprocessor features sparingly!
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* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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#include "ld.common"
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#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
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#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
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#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
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#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
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#else
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#define ESP_BOOTLOADER_RESERVE_RTC 0
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#endif
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/**
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* physical memory is mapped twice to the vritual address (IRAM and DRAM).
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* `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
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*/
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#define SRAM_IRAM_START 0x40800000
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#define SRAM_DRAM_START 0x40800000
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#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
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#define SRAM_DRAM_END 0x40880000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
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#define SRAM_IRAM_ORG (SRAM_IRAM_START)
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#define SRAM_DRAM_ORG (SRAM_DRAM_START)
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#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/*
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* IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB
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*/
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#define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8)
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#endif
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#if CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE
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ASSERT((CONFIG_ESP32C6_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.")
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#define DRAM0_0_SEG_LEN CONFIG_ESP3C6_FIXED_STATIC_RAM_SIZE
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#else
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#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
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#endif // CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE
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MEMORY
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{
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/**
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* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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* are connected to the data port of the CPU and eg allow byte-wise access.
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*/
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/* IRAM for PRO CPU. */
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iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped instruction data */
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irom_seg (RX) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
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/**
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* (0x20 offset above is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
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*/
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dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped constant data */
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drom_seg (R) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
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/* (See irom_seg for meaning of 0x20 offset in the above.) */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
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*/
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#if CONFIG_ULP_COPROC_ENABLED
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lp_ram_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
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len = 0x4000 - CONFIG_ULP_COPROC_RESERVE_MEM
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#else
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lp_ram_seg(RW) : org = 0x50000000 , len = 0x4000
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#endif // CONFIG_ULP_COPROC_ENABLED
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}
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#if CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE
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/* static data ends at defined address */
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_static_data_end = 0x40820000 + DRAM0_0_SEG_LEN;
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#else
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_static_data_end = _bss_end;
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#endif // CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000;
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_data_seg_org = ORIGIN(rtc_data_seg);
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/**
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* The lines below define location alias for .rtc.data section
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* C6 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section
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* Thus, the following region segments are not configurable like on other targets
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*/
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REGION_ALIAS("rtc_iram_seg", lp_ram_seg );
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REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
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REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
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REGION_ALIAS("rtc_data_location", rtc_iram_seg );
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_code_seg", irom_seg);
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#else
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REGION_ALIAS("default_code_seg", iram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_rodata_seg", drom_seg);
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#else
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REGION_ALIAS("default_rodata_seg", dram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
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* also be first in the segment.
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*/
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
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".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
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#endif
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#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
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ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
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ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
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#endif
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