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111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ROM_EFUSE_H_
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#define _ROM_EFUSE_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup efuse_APIs efuse APIs
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* @brief ESP32 efuse read/write APIs
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* @attention
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*
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*/
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/** @addtogroup efuse_APIs
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* @{
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*/
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/**
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* @brief Do a efuse read operation, to update the efuse value to efuse read registers.
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*
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* @param null
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*
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* @return null
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*/
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void ets_efuse_read_op(void);
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/**
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* @brief Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
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*
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* @param null
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*
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* @return null
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*/
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void ets_efuse_program_op(void);
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/**
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* @brief Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature.
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* It can be used to test the external xtal frequency, do not touch this efuse field.
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*
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* @param null
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*
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* @return u32: 1 for 100KHZ, range is 0 to 255.
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*/
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uint32_t ets_efuse_get_8M_clock(void);
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/**
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* @brief Read spi flash pin configuration from Efuse
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*
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* @return
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* - 0 for default SPI pins.
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* - 1 for default HSPI pins.
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* - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
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* EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
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* WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
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*/
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uint32_t ets_efuse_get_spiconfig(void);
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#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
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#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
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#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
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#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
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#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
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#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f
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#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6
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#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
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#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f
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#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12
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#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
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#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f
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#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18
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#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
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#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f
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#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24
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#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
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/**
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* @brief A crc8 algorithm used in efuse check.
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*
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* @param unsigned char const *p : Pointer to original data.
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*
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* @param unsigned int len : Data length in byte.
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*
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* @return unsigned char: Crc value.
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*/
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unsigned char esp_crc8(unsigned char const *p, unsigned int len);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_EFUSE_H_ */
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