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103 lines
3.6 KiB
C
103 lines
3.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _CACHE_MEMORY_H_
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#define _CACHE_MEMORY_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "esp32c2/rom/cache.h"
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/*IRAM0 is connected with Cache IBUS0*/
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#define MMU_PAGE_MODE MMU_Get_Page_Mode()
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#define IRAM0_ADDRESS_LOW 0x40000000
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#define IRAM0_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH
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#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
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#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + (0x100000 << (MMU_PAGE_MODE)))
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/*DRAM0 is connected with Cache DBUS0*/
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#define DRAM0_ADDRESS_LOW 0x3C000000
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#define DRAM0_ADDRESS_HIGH 0x40000000
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#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000
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#define DRAM0_CACHE_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_LOW + (0x100000 << (MMU_PAGE_MODE)))
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#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
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#define ESP_CACHE_TEMP_ADDR 0x3C000000
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#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
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#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
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#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
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#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
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#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
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#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
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#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
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#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
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//IDF-3821
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// #define MMU_SIZE 0x100
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#define CACHE_IBUS 0
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#define CACHE_IBUS_MMU_START 0
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#define CACHE_IBUS_MMU_END 0x100
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#define CACHE_DBUS 1
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#define CACHE_DBUS_MMU_START 0
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#define CACHE_DBUS_MMU_END 0x100
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#define CACHE_IROM_MMU_START 0
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
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#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
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#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
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#define CACHE_DROM_MMU_MAX_END 0x100
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#define ICACHE_MMU_SIZE 0x100
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#define DCACHE_MMU_SIZE 0x100
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#define MMU_BUS_START(i) 0
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#define MMU_BUS_SIZE(i) 0x100
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#define MMU_INVALID BIT(6)
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#define MMU_TYPE 0
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#define MMU_ACCESS_FLASH 0
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#define CACHE_MAX_SYNC_NUM 0x400000
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#define CACHE_MAX_LOCK_NUM 0x8000
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#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
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#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
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#define MMU_TABLE_INVALID_VAL MMU_INVALID
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#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
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#define MMU_ADDRESS_MASK (MMU_TABLE_INVALID_VAL - 1)
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#define MMU_PAGE_SIZE (0x4000 << (MMU_PAGE_MODE))
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#define INVALID_PHY_PAGE (MMU_PAGE_SIZE - 1)
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#define BUS_ADDR_SIZE (0x100000 << (MMU_PAGE_MODE))
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#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
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#define BUS_PMS_MASK 0xffffff
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#define CACHE_ICACHE_LOW_SHIFT 0
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#define CACHE_ICACHE_HIGH_SHIFT 2
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#define CACHE_DCACHE_LOW_SHIFT 4
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#define CACHE_DCACHE_HIGH_SHIFT 6
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#define CACHE_MEMORY_IBANK0_ADDR 0x4037C000
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#ifdef __cplusplus
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}
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#endif
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#endif /*_CACHE_MEMORY_H_ */
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