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182e937c5a
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
25 lines
741 B
Plaintext
25 lines
741 B
Plaintext
choice ESP_DEFAULT_CPU_FREQ_MHZ
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prompt "CPU frequency"
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default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
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default ESP_DEFAULT_CPU_FREQ_MHZ_160
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help
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CPU frequency to be set on application startup.
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config ESP_DEFAULT_CPU_FREQ_MHZ_40
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bool "40 MHz"
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depends on IDF_ENV_FPGA
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config ESP_DEFAULT_CPU_FREQ_MHZ_80
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bool "80 MHz"
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config ESP_DEFAULT_CPU_FREQ_MHZ_120
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bool "120 MHz"
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config ESP_DEFAULT_CPU_FREQ_MHZ_160
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bool "160 MHz"
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endchoice
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config ESP_DEFAULT_CPU_FREQ_MHZ
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int
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default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
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default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80
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default 120 if ESP_DEFAULT_CPU_FREQ_MHZ_120
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default 160 if ESP_DEFAULT_CPU_FREQ_MHZ_160
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