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https://github.com/espressif/esp-idf.git
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74 lines
2.0 KiB
C
74 lines
2.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/cache_ll.h"
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#include "hal/cache_hal.h"
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static uint32_t s_cache_status[2];
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/**
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* On ESP32, The cache_hal_suspend()/cache_hal_resume() are replacements
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* for Cache_Read_Disable()/Cache_Read_Enable() in ROM.
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* There's a bug that Cache_Read_Disable requires a call to Cache_Flush
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* before Cache_Read_Enable, even if cached data was not modified.
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*/
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void cache_hal_suspend(uint32_t cache_level, cache_type_t type)
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{
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s_cache_status[0] = cache_ll_l1_get_enabled_bus(0);
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cache_ll_l1_disable_cache(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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s_cache_status[1] = cache_ll_l1_get_enabled_bus(1);
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cache_ll_l1_disable_cache(1);
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#endif
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}
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void cache_hal_resume(uint32_t cache_level, cache_type_t type)
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{
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cache_ll_l1_enable_cache(0);
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cache_ll_l1_enable_bus(0, s_cache_status[0]);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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cache_ll_l1_enable_cache(1);
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cache_ll_l1_enable_bus(1, s_cache_status[1]);
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#endif
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}
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bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type)
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{
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bool result = cache_ll_l1_is_cache_enabled(0, CACHE_TYPE_ALL);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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result = result && cache_ll_l1_is_cache_enabled(1, CACHE_TYPE_ALL);
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#endif
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return result;
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}
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bool cache_hal_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
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{
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if (!out_level || !out_id) {
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return false;
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}
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return cache_ll_vaddr_to_cache_level_id(vaddr_start, len, out_level, out_id);
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}
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uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type)
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{
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HAL_ASSERT(cache_level <= CACHE_LL_LEVEL_NUMS);
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uint32_t line_size = 0;
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if (cache_level == CACHE_LL_LEVEL_EXT_MEM) {
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line_size = 4;
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}
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return line_size;
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}
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bool cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size)
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{
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//esp32 doesn't support invalidate certain addr
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abort();
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}
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