esp-idf/components/riscv
Liu Xiao Yu 52175a6548 Merge branch 'refactor/supplement_plic_intr_rv_util_apis' into 'master'
refactor(intr): add plic and intc interrupt rv util apis

See merge request espressif/esp-idf!33244
2024-09-12 15:28:24 +08:00
..
include Merge branch 'refactor/supplement_plic_intr_rv_util_apis' into 'master' 2024-09-12 15:28:24 +08:00
ld refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
CMakeLists.txt refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
instruction_decode.c refactor(tools): Tidy up core component files copyright ignore 2024-01-22 18:07:35 +08:00
interrupt_clic.c refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
interrupt_intc.c refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
interrupt_plic.c refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
interrupt.c feat(intr): basic interrupt/freertos support for C61 2024-06-12 09:25:47 +08:00
linker.lf riscv: moved some interrupt functions from IRAM to flash 2023-04-10 12:21:11 +08:00
project_include.cmake build: Adds support for universal Clang toolchain 2022-11-23 13:25:16 +03:00
vectors_clic.S feat(system): esp32p4: support hw stack guard 2024-03-21 14:30:21 +04:00
vectors_intc.S fix: mark .exception_vectors* as executable and allocatable 2024-03-21 08:53:09 +01:00
vectors.S fix(riscv): make HWLP feature use direct saving of lazy saving 2024-05-21 17:27:46 +08:00