mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
83dd60307f
- In case of AXI-DMA, the DMA descriptors need to be 8 bytes aligned lldesc_t do not satify this condition thus we need to replace it with dma_descriptor_t (align(4) and align(8)) in esp_crypto_shared_gdma. - Added new shared gdma start API that supports the dma_descriptor_t DMA descriptor. - Added some generic dma descriptor macros and helper functions - replace lldesc_t with dma_descriptor_t
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "hal/dma_types.h"
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#include "soc/gdma_channel.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#if (SOC_AES_SUPPORT_DMA) && (SOC_SHA_SUPPORT_DMA)
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#if (SOC_AES_GDMA) && (SOC_SHA_GDMA)
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#if (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AHB) && (SOC_GDMA_TRIG_PERIPH_SHA0_BUS == SOC_GDMA_BUS_AHB)
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#define DMA_DESC_MEM_ALIGN_SIZE 4
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typedef dma_descriptor_align4_t crypto_dma_desc_t;
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#elif (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AXI) && (SOC_GDMA_TRIG_PERIPH_SHA0_BUS == SOC_GDMA_BUS_AXI)
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#define DMA_DESC_MEM_ALIGN_SIZE 8
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typedef dma_descriptor_align8_t crypto_dma_desc_t;
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#else
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#error "As we support a shared crypto GDMA layer for the AES and the SHA peripheral, both the peripherals must use the same GDMA bus"
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#endif /* (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AHB) && (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AHB) */
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#elif (SOC_AES_CRYPTO_DMA) && (SOC_SHA_CRYPTO_DMA)
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#define DMA_DESC_MEM_ALIGN_SIZE 4
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typedef dma_descriptor_align4_t crypto_dma_desc_t;
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#endif /* (SOC_AES_GDMA) && (SOC_SHA_GDMA) */
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#endif /* (SOC_AES_SUPPORT_DMA) && (SOC_SHA_SUPPORT_DMA) */
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#ifdef __cplusplus
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}
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#endif
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