mirror of
https://github.com/espressif/esp-idf.git
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4d8a0cce29
This commit enables ULP FSM support for esp32s3 and updates ULP FSM code flow for other chips. It adds C Macro support for the ULP FSM instruction set on esp32s2 and esp32s3. The unit tests are also updated to test ULP FSM on ep32s2 and esp32s3.
76 lines
2.7 KiB
C
76 lines
2.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdlib.h>
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#include "esp_err.h"
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#include "esp_log.h"
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#include "ulp_common.h"
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#include "esp_private/esp_clk.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#if CONFIG_IDF_TARGET_ESP32
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#define ULP_FSM_PREPARE_SLEEP_CYCLES 2 /*!< Cycles spent by FSM preparing ULP for sleep */
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#define ULP_FSM_WAKEUP_SLEEP_CYCLES 2 /*!< Cycles spent by FSM waking up ULP from sleep */
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#endif
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esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us)
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{
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if (period_index > 4) {
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return ESP_ERR_INVALID_ARG;
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}
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uint64_t period_us_64 = period_us;
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#if CONFIG_IDF_TARGET_ESP32
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uint64_t period_cycles = (period_us_64 << RTC_CLK_CAL_FRACT) / esp_clk_slowclk_cal_get();
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uint64_t min_sleep_period_cycles = ULP_FSM_PREPARE_SLEEP_CYCLES
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+ ULP_FSM_WAKEUP_SLEEP_CYCLES
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+ REG_GET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT);
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if (period_cycles < min_sleep_period_cycles) {
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period_cycles = min_sleep_period_cycles;
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ESP_LOGW("ulp", "Sleep period clipped to minimum of %d cycles", (uint32_t) min_sleep_period_cycles);
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} else {
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period_cycles -= min_sleep_period_cycles;
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}
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REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t),
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SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles);
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#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
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rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
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rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
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rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
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rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
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if (slow_clk_freq == (rtc_slow_freq_x32k)) {
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cal_clk = RTC_CAL_32K_XTAL;
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} else if (slow_clk_freq == rtc_slow_freq_8MD256) {
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cal_clk = RTC_CAL_8MD256;
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}
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uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
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uint64_t period_cycles = rtc_time_us_to_slowclk(period_us_64, slow_clk_period);
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REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_1_REG, RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE, ((uint32_t)period_cycles));
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#endif
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return ESP_OK;
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}
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void ulp_timer_stop(void)
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{
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#if CONFIG_IDF_TARGET_ESP32
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CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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#else
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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#endif
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}
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void ulp_timer_resume(void)
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{
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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#else
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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#endif
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}
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