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https://github.com/espressif/esp-idf.git
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c331c85318
For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required. Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be cleared. When system clock switches up, the delays should be restored.
513 lines
20 KiB
C
513 lines
20 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdlib.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_log.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/io_mux_reg.h"
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#include "esp_private/spi_flash_os.h"
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#include "soc/soc.h"
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/spi_timing_config.h"
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#include "esp32s3/rom/cache.h"
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#endif
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#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(*(arr)))
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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const static char *TAG = "MSPI Timing";
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static spi_timing_tuning_param_t s_flash_best_timing_tuning_config;
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static spi_timing_tuning_param_t s_psram_best_timing_tuning_config;
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#endif
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/*------------------------------------------------------------------------------
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* Common settings
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*----------------------------------------------------------------------------*/
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void spi_timing_set_pin_drive_strength(void)
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{
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//For now, set them all to 3. Need to check after QVL test results are out. TODO: IDF-3663
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//Set default clk
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SET_PERI_REG_MASK(SPI_MEM_DATE_REG(0), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
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REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, 3);
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REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, 3);
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//Set default mspi d0 ~ d7, dqs pin drive strength
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uint32_t regs[] = {IO_MUX_GPIO27_REG, IO_MUX_GPIO28_REG,
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IO_MUX_GPIO31_REG, IO_MUX_GPIO32_REG,
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IO_MUX_GPIO33_REG, IO_MUX_GPIO34_REG,
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IO_MUX_GPIO35_REG, IO_MUX_GPIO36_REG,
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IO_MUX_GPIO37_REG};
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for (int i = 0; i < ARRAY_SIZE(regs); i++) {
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PIN_SET_DRV(regs[i], 3);
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}
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}
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/*------------------------------------------------------------------------------
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* Static functions to get clock configs
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*----------------------------------------------------------------------------*/
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static spi_timing_config_core_clock_t get_mspi_core_clock(void)
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{
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return spi_timing_config_get_core_clock();
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}
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static uint32_t get_flash_clock_divider(void)
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{
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#if CONFIG_ESPTOOLPY_FLASHFREQ_20M
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return SPI_TIMING_CORE_CLOCK_MHZ / 20;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
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return SPI_TIMING_CORE_CLOCK_MHZ / 40;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
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return SPI_TIMING_CORE_CLOCK_MHZ / 80;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_120M
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return SPI_TIMING_CORE_CLOCK_MHZ / 120;
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#else
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abort();
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#endif
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}
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static uint32_t get_psram_clock_divider(void)
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{
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#if CONFIG_SPIRAM_SPEED_40M
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return SPI_TIMING_CORE_CLOCK_MHZ / 40;
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#elif CONFIG_SPIRAM_SPEED_80M
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return SPI_TIMING_CORE_CLOCK_MHZ / 80;
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#elif CONFIG_SPIRAM_SPEED_120M
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return SPI_TIMING_CORE_CLOCK_MHZ / 120;
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#else
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//Will enter this branch only if PSRAM is not enable
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return 0;
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#endif
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}
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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/*------------------------------------------------------------------------------
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* Static functions to do timing tuning
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*----------------------------------------------------------------------------*/
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/**
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* Set timing tuning regs, in order to get successful sample points
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*/
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static void init_spi1_for_tuning(bool is_flash)
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{
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//Get required core clock and module clock settings
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spi_timing_config_core_clock_t core_clock = get_mspi_core_clock();
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//Set SPI1 core clock. SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
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spi_timing_config_set_core_clock(0, core_clock);
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//Set SPI1 module clock as required
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if (is_flash) {
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uint32_t flash_div = get_flash_clock_divider();
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spi_timing_config_set_flash_clock(1, flash_div);
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//Power on HCLK
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REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CLK_ENA);
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} else {
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//We use SPI1 Flash to tune PSRAM, PSRAM timing related regs do nothing on SPI1
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uint32_t psram_div = get_psram_clock_divider();
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spi_timing_config_set_flash_clock(1, psram_div);
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//Power on HCLK
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REG_SET_BIT(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(0), SPI_MEM_SPI_SMEM_TIMING_CLK_ENA);
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}
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}
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/**
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* We use different SPI1 timing tuning config to read data to see if current MSPI sampling is successful.
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* The sampling result will be stored in an array. In this array, successful item will be 1, failed item will be 0.
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*/
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static void sweep_for_success_sample_points(uint8_t *reference_data, const spi_timing_config_t *config, bool is_flash, uint8_t *out_array)
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{
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uint32_t config_idx = 0;
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uint8_t read_data[SPI_TIMING_TEST_DATA_LEN] = {0};
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for (config_idx = 0; config_idx < config->available_config_num; config_idx++) {
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memset(read_data, 0, SPI_TIMING_TEST_DATA_LEN);
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#if SPI_TIMING_FLASH_NEEDS_TUNING
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if (is_flash) {
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spi_timing_config_flash_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num);
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spi_timing_config_flash_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len);
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spi_timing_config_flash_read_data(1, read_data, SPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(read_data));
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}
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#endif
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#if SPI_TIMING_PSRAM_NEEDS_TUNING
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if (!is_flash) {
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spi_timing_config_psram_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num);
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spi_timing_config_psram_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len);
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spi_timing_config_psram_read_data(1, read_data, SPI_TIMING_PSRAM_TEST_DATA_ADDR, SPI_TIMING_TEST_DATA_LEN);
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}
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#endif
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if (memcmp(reference_data, read_data, sizeof(read_data)) == 0) {
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out_array[config_idx] = 1;
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}
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}
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}
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/**
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* Find consecutive successful sampling points.
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* e.g. array: {1, 1, 0, 0, 1, 1, 1, 0}
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* out_length: 3
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* outout_end_index: 6
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*/
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static void find_max_consecutive_success_points(uint8_t *array, uint32_t size, uint32_t *out_length, uint32_t *out_end_index)
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{
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uint32_t max = 0;
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uint32_t match_num = 0;
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uint32_t i = 0;
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uint32_t end = 0;
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while (i < size) {
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if (array[i]) {
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match_num++;
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} else {
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if (match_num > max) {
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max = match_num;
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end = i - 1;
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}
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match_num = 0;
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}
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i++;
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}
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*out_length = match_num > max ? match_num : max;
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*out_end_index = match_num == size ? size : end;
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}
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#if SPI_TIMING_FLASH_DTR_MODE || SPI_TIMING_PSRAM_DTR_MODE
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static uint32_t select_best_tuning_config_dtr(spi_timing_config_t *config, uint32_t consecutive_length, uint32_t end)
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{
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#if (SPI_TIMING_CORE_CLOCK_MHZ == 160)
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//Core clock 160M DTR best point scheme
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uint32_t best_point;
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//Define these magic number in macros in `spi_timing_config.h`. TODO: IDF-3663
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if (consecutive_length <= 2 || consecutive_length >= 6) {
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//tuning is FAIL, select default point, and generate a warning
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best_point = config->default_config_id;
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ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point);
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} else if (consecutive_length <= 4) {
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//consecutive length : 3 or 4
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best_point = end - 1;
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ESP_EARLY_LOGD(TAG,"tuning success, best point is index %d", best_point);
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} else {
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//consecutive point list length equals 5
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best_point = end - 2;
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ESP_EARLY_LOGD(TAG,"tuning success, best point is index %d", best_point);
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}
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return best_point;
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#else
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//won't reach here
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abort();
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#endif
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}
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#endif
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#if SPI_TIMING_FLASH_STR_MODE || SPI_TIMING_PSRAM_STR_MODE
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static uint32_t select_best_tuning_config_str(spi_timing_config_t *config, uint32_t consecutive_length, uint32_t end)
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{
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#if (SPI_TIMING_CORE_CLOCK_MHZ == 120 || SPI_TIMING_CORE_CLOCK_MHZ == 240)
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//STR best point scheme
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uint32_t best_point;
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if (consecutive_length <= 2|| consecutive_length >= 5) {
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//tuning is FAIL, select default point, and generate a warning
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best_point = config->default_config_id;
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ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point);
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} else {
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//consecutive length : 3 or 4
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best_point = end - consecutive_length / 2;
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ESP_EARLY_LOGD(TAG,"tuning success, best point is index %d", best_point);
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}
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return best_point;
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#else
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//won't reach here
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abort();
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#endif
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}
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#endif
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static void select_best_tuning_config(spi_timing_config_t *config, uint32_t consecutive_length, uint32_t end, bool is_flash)
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{
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uint32_t best_point = 0;
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if (is_flash) {
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#if SPI_TIMING_FLASH_DTR_MODE
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best_point = select_best_tuning_config_dtr(config, consecutive_length, end);
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#elif SPI_TIMING_FLASH_STR_MODE
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best_point = select_best_tuning_config_str(config, consecutive_length, end);
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#endif
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s_flash_best_timing_tuning_config = config->tuning_config_table[best_point];
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} else {
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#if SPI_TIMING_PSRAM_DTR_MODE
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best_point = select_best_tuning_config_dtr(config, consecutive_length, end);
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#elif SPI_TIMING_PSRAM_STR_MODE
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best_point = select_best_tuning_config_str(config, consecutive_length, end);
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#endif
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s_psram_best_timing_tuning_config = config->tuning_config_table[best_point];
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}
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}
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static void do_tuning(uint8_t *reference_data, spi_timing_config_t *timing_config, bool is_flash)
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{
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/**
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* We use SPI1 to tune the timing:
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* 1. Get all SPI1 sampling results.
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* 2. Find the longest consecutive successful sampling points from the result above.
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* 3. The middle one will be the best sampling point.
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*/
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uint32_t consecutive_length = 0;
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uint32_t last_success_point = 0;
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uint8_t sample_result[SPI_TIMING_CONFIG_NUM_DEFAULT] = {0};
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init_spi1_for_tuning(is_flash);
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sweep_for_success_sample_points(reference_data, timing_config, is_flash, sample_result);
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find_max_consecutive_success_points(sample_result, SPI_TIMING_CONFIG_NUM_DEFAULT, &consecutive_length, &last_success_point);
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select_best_tuning_config(timing_config, consecutive_length, last_success_point, is_flash);
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}
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#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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/*------------------------------------------------------------------------------
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* FLASH Timing Tuning
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*----------------------------------------------------------------------------*/
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#if SPI_TIMING_FLASH_NEEDS_TUNING
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static void get_flash_tuning_configs(spi_timing_config_t *config)
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{
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#if SPI_TIMING_FLASH_DTR_MODE
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#define FLASH_MODE DTR_MODE
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#else //SPI_TIMING_FLASH_STR_MODE
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#define FLASH_MODE STR_MODE
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#endif
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#if CONFIG_ESPTOOLPY_FLASHFREQ_20M
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*config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 20, FLASH_MODE);
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
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*config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 40, FLASH_MODE);
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
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*config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 80, FLASH_MODE);
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_120M
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*config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 120, FLASH_MODE);
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#endif
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#undef FLASH_MODE
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}
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void spi_timing_flash_tuning(void)
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{
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ESP_EARLY_LOGW("FLASH", "DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version.");
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/**
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* set SPI01 related regs to 20mhz configuration, to get reference data from FLASH
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* see detailed comments in this function (`spi_timing_enter_mspi_low_speed_mode`)
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*/
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spi_timing_enter_mspi_low_speed_mode(true);
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//Disable the variable dummy mode when doing timing tuning
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CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY); //GD flash will read error in variable mode with 20MHz
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uint8_t reference_data[SPI_TIMING_TEST_DATA_LEN] = {0};
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spi_timing_config_flash_read_data(1, reference_data, SPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(reference_data));
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spi_timing_config_t timing_configs = {0};
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get_flash_tuning_configs(&timing_configs);
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do_tuning(reference_data, &timing_configs, true);
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spi_timing_enter_mspi_high_speed_mode(true);
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}
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#else
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void spi_timing_flash_tuning(void)
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{
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//Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned
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}
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#endif //SPI_TIMING_FLASH_NEEDS_TUNING
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/*------------------------------------------------------------------------------
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* PSRAM Timing Tuning
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*----------------------------------------------------------------------------*/
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#if SPI_TIMING_PSRAM_NEEDS_TUNING
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static void get_psram_tuning_configs(spi_timing_config_t *config)
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{
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#if SPI_TIMING_PSRAM_DTR_MODE
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#define PSRAM_MODE DTR_MODE
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#else //SPI_TIMING_PSRAM_STR_MODE
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#define PSRAM_MODE STR_MODE
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#endif
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#if CONFIG_SPIRAM_SPEED_40M
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*config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 40, PSRAM_MODE);
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#elif CONFIG_SPIRAM_SPEED_80M
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*config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 80, PSRAM_MODE);
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#elif CONFIG_SPIRAM_SPEED_120M
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*config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 120, PSRAM_MODE);
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#endif
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#undef PSRAM_MODE
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}
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void spi_timing_psram_tuning(void)
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{
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ESP_EARLY_LOGW("PSRAM", "DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version.");
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/**
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* set SPI01 related regs to 20mhz configuration, to write reference data to PSRAM
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* see detailed comments in this function (`spi_timing_enter_mspi_low_speed_mode`)
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*/
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spi_timing_enter_mspi_low_speed_mode(true);
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// write data into psram, used to do timing tuning test.
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uint8_t reference_data[SPI_TIMING_TEST_DATA_LEN];
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for (int i=0; i < SPI_TIMING_TEST_DATA_LEN/4; i++) {
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((uint32_t *)reference_data)[i] = 0xa5ff005a;
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}
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spi_timing_config_psram_write_data(1, reference_data, SPI_TIMING_PSRAM_TEST_DATA_ADDR, SPI_TIMING_TEST_DATA_LEN);
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spi_timing_config_t timing_configs = {0};
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get_psram_tuning_configs(&timing_configs);
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//Disable the variable dummy mode when doing timing tuning
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CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY);
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//Get required config, and set them to PSRAM related registers
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do_tuning(reference_data, &timing_configs, false);
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spi_timing_enter_mspi_high_speed_mode(true);
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}
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#else
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void spi_timing_psram_tuning(void)
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{
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//Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned
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}
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#endif //SPI_TIMING_PSRAM_NEEDS_TUNING
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/*------------------------------------------------------------------------------
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* APIs to make SPI0 (and SPI1) FLASH work for high/low freq
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*----------------------------------------------------------------------------*/
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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static void clear_timing_tuning_regs(bool control_spi1)
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{
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spi_timing_config_flash_set_din_mode_num(0, 0, 0); //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg
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spi_timing_config_flash_set_extra_dummy(0, 0);
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if (control_spi1) {
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spi_timing_config_flash_set_extra_dummy(1, 0);
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} else {
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//Won't touch SPI1 registers
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}
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}
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#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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void spi_timing_enter_mspi_low_speed_mode(bool control_spi1)
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{
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/**
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* Here we are going to slow the SPI1 frequency to 20Mhz, so we need to set SPI1 din_num and din_mode regs.
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*
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* Because SPI0 and SPI1 share the din_num and din_mode regs, so if we clear SPI1 din_num and din_mode to
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* 0, if the SPI0 flash module clock is still in high freq, it may not work correctly.
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*
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* Therefore, here we need to slow both the SPI0 and SPI1 and related timing tuning regs to 20Mhz configuration.
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*/
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|
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//Switch SPI1 and SPI0 clock as 20MHz, set its SPIMEM core clock as 80M and set clock division as 4
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spi_timing_config_set_core_clock(0, SPI_TIMING_CONFIG_CORE_CLOCK_80M); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
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spi_timing_config_set_flash_clock(0, 4);
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if (control_spi1) {
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//After tuning, won't touch SPI1 again
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spi_timing_config_set_flash_clock(1, 4);
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}
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|
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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clear_timing_tuning_regs(control_spi1);
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#endif
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}
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|
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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static void set_timing_tuning_regs_as_required(bool control_spi1)
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|
{
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//SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg
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spi_timing_config_flash_set_din_mode_num(0, s_flash_best_timing_tuning_config.spi_din_mode, s_flash_best_timing_tuning_config.spi_din_num);
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spi_timing_config_flash_set_extra_dummy(0, s_flash_best_timing_tuning_config.extra_dummy_len);
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|
if (control_spi1) {
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spi_timing_config_flash_set_extra_dummy(1, s_flash_best_timing_tuning_config.extra_dummy_len);
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|
}
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|
|
|
spi_timing_config_psram_set_din_mode_num(0, s_psram_best_timing_tuning_config.spi_din_mode, s_psram_best_timing_tuning_config.spi_din_num);
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spi_timing_config_psram_set_extra_dummy(0, s_psram_best_timing_tuning_config.extra_dummy_len);
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|
}
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|
#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
|
|
|
|
/**
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|
* Set SPI0 FLASH and PSRAM module clock, din_num, din_mode and extra dummy,
|
|
* according to the configuration got from timing tuning function (`calculate_best_flash_tuning_config`).
|
|
* iF control_spi1 == 1, will also update SPI1 timing registers. Should only be set to 1 when do tuning.
|
|
*
|
|
* This function should always be called after `spi_timing_flash_tuning` or `calculate_best_flash_tuning_config`
|
|
*/
|
|
void spi_timing_enter_mspi_high_speed_mode(bool control_spi1)
|
|
{
|
|
spi_timing_config_core_clock_t core_clock = get_mspi_core_clock();
|
|
uint32_t flash_div = get_flash_clock_divider();
|
|
uint32_t psram_div = get_psram_clock_divider();
|
|
|
|
//Set SPI01 core clock
|
|
spi_timing_config_set_core_clock(0, core_clock); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
|
|
//Set FLASH module clock
|
|
spi_timing_config_set_flash_clock(0, flash_div);
|
|
if (control_spi1) {
|
|
spi_timing_config_set_flash_clock(1, flash_div);
|
|
}
|
|
//Set PSRAM module clock
|
|
spi_timing_config_set_psram_clock(0, psram_div);
|
|
|
|
#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
|
|
set_timing_tuning_regs_as_required(true);
|
|
#endif
|
|
}
|
|
|
|
void spi_timing_change_speed_mode_cache_safe(bool switch_down)
|
|
{
|
|
Cache_Freeze_ICache_Enable(1);
|
|
Cache_Freeze_DCache_Enable(1);
|
|
if (switch_down) {
|
|
//enter MSPI low speed mode, extra delays should be removed
|
|
spi_timing_enter_mspi_low_speed_mode(false);
|
|
} else {
|
|
//enter MSPI high speed mode, extra delays should be considered
|
|
spi_timing_enter_mspi_high_speed_mode(false);
|
|
}
|
|
Cache_Freeze_DCache_Disable();
|
|
Cache_Freeze_ICache_Disable();
|
|
}
|
|
|
|
/*------------------------------------------------------------------------------
|
|
* APIs to inform SPI1 Flash driver of necessary timing configurations
|
|
*----------------------------------------------------------------------------*/
|
|
bool spi_timing_is_tuned(void)
|
|
{
|
|
#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
|
|
return true;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
|
|
void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config)
|
|
{
|
|
// Get clock configuration directly from system.
|
|
out_timing_config->clock_config.spimem.val = spi_timing_config_get_flash_clock_reg();
|
|
|
|
// Get extra dummy length here. Therefore, no matter what freq, or mode.
|
|
// If it needs tuning, it will return correct extra dummy len. If no tuning, it will return 0.
|
|
|
|
out_timing_config->extra_dummy = s_flash_best_timing_tuning_config.extra_dummy_len;
|
|
|
|
// Get CS setup/hold value here.
|
|
spi_timing_config_get_cs_timing(&out_timing_config->cs_setup, &out_timing_config->cs_hold);
|
|
}
|
|
#else
|
|
void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config)
|
|
{
|
|
// This function shouldn't be called if timing tuning is not used.
|
|
abort();
|
|
}
|
|
#endif // SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
|