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esp-idf/components/freertos/port/riscv
History
Omar Chebib b2ddedb941 FreeRTOS: Make the default stack alignment 16 for Xtensa
2022-12-02 15:20:09 +08:00
..
include/freertos freertos: Add portTRY_ENTRY_CRITICAL() and deprecate legacy spinlock fucntions 2021-11-22 18:42:10 +08:00
port.c FreeRTOS: Make the default stack alignment 16 for Xtensa 2022-12-02 15:20:09 +08:00
portasm.S core: fix cases where riscv SP were not 16 byte aligned 2021-02-19 11:26:21 +08:00