Sachin Parekh 301dacfb33 Exception handlers for LoadStoreError and LoadStoreAlignmentError ... Configurable option to use IRAM as byte accessible memory (in single core mode) using load-store (non-word aligned and non-word size IRAM access specific) exception handlers. This allows to use IRAM for use-cases where certain performance penalty (upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration option has been provided to redirect mbedTLS specific in-out content length buffers to IRAM (in single core mode), allows to save 20KB per TLS connection.		2020-02-26 20:21:59 +08:00
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esp_heap_caps_init.h	tools: Mass fixing of empty prototypes (for -Wstrict-prototypes)	2019-08-01 16:28:56 +07:00
esp_heap_caps.h	Exception handlers for LoadStoreError and LoadStoreAlignmentError	2020-02-26 20:21:59 +08:00
esp_heap_task_info.h	heap: Add task tracking option for heap usage monitoring	2018-02-20 10:32:06 +11:00
esp_heap_trace.h	heap: Separate standalone and common part of tracing module	2019-04-01 15:56:15 +03:00
heap_trace.inc	heap: recognize 0x40000000 as an address terminating the backtrace	2020-01-02 18:42:46 +01:00
multi_heap.h	heap/multi_heap: added initial implementation of aligned alloc function	2020-01-10 10:05:27 -03:00