mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
421 lines
12 KiB
C
421 lines
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: configuration register */
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/** Type of bt_select register
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* GPIO bit select register
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*/
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typedef union {
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struct {
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/** bt_sel : R/W; bitpos: [31:0]; default: 0;
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* GPIO bit select register
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*/
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uint32_t bt_sel:32;
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};
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uint32_t val;
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} gpio_bt_select_reg_t;
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/** Type of out register
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* GPIO output register for GPIO0-29
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*/
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typedef union {
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struct {
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/** out_data_orig : R/W/WS/WC; bitpos: [29:0]; default: 0;
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* GPIO output register for GPIO0-29
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*/
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uint32_t out_data_orig:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_out_reg_t;
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/** Type of out_w1ts register
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* GPIO output set register for GPIO0-29
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*/
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typedef union {
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struct {
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/** out_w1ts : WT; bitpos: [29:0]; default: 0;
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* GPIO output set register for GPIO0-29
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*/
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uint32_t out_w1ts:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_out_w1ts_reg_t;
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/** Type of out_w1tc register
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* GPIO output clear register for GPIO0-29
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*/
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typedef union {
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struct {
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/** out_w1tc : WT; bitpos: [29:0]; default: 0;
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* GPIO output clear register for GPIO0-29
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*/
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uint32_t out_w1tc:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_out_w1tc_reg_t;
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/** Type of sdio_select register
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* GPIO sdio select register
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*/
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typedef union {
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struct {
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/** sdio_sel : R/W; bitpos: [7:0]; default: 0;
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* GPIO sdio select register
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*/
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uint32_t sdio_sel:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} gpio_sdio_select_reg_t;
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/** Type of enable register
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* GPIO output enable register for GPIO0-29
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*/
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typedef union {
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struct {
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/** enable_data : R/W/SS; bitpos: [29:0]; default: 0;
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* GPIO output enable register for GPIO0-29
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*/
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uint32_t enable_data:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_enable_reg_t;
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/** Type of enable_w1ts register
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* GPIO output enable set register for GPIO0-29
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*/
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typedef union {
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struct {
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/** enable_w1ts : WT; bitpos: [29:0]; default: 0;
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* GPIO output enable set register for GPIO0-29
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*/
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uint32_t enable_w1ts:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_enable_w1ts_reg_t;
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/** Type of enable_w1tc register
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* GPIO output enable clear register for GPIO0-29
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*/
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typedef union {
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struct {
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/** enable_w1tc : WT; bitpos: [29:0]; default: 0;
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* GPIO output enable clear register for GPIO0-29
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*/
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uint32_t enable_w1tc:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_enable_w1tc_reg_t;
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/** Type of strap register
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* pad strapping register
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*/
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typedef union {
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struct {
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/** strapping : RO; bitpos: [15:0]; default: 0;
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* pad strapping register
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*/
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uint32_t strapping:16;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} gpio_strap_reg_t;
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/** Type of in register
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* GPIO input register for GPIO0-29
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*/
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typedef union {
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struct {
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/** in_data_next : RO; bitpos: [29:0]; default: 0;
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* GPIO input register for GPIO0-29
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*/
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uint32_t in_data_next:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_in_reg_t;
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/** Type of status register
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* GPIO interrupt status register for GPIO0-29
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*/
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typedef union {
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struct {
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/** status_interrupt : R/W/SS; bitpos: [29:0]; default: 0;
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* GPIO interrupt status register for GPIO0-29
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*/
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uint32_t status_interrupt:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_status_reg_t;
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/** Type of status_w1ts register
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* GPIO interrupt status set register for GPIO0-29
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*/
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typedef union {
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struct {
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/** status_w1ts : WT; bitpos: [29:0]; default: 0;
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* GPIO interrupt status set register for GPIO0-29
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*/
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uint32_t status_w1ts:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_status_w1ts_reg_t;
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/** Type of status_w1tc register
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* GPIO interrupt status clear register for GPIO0-29
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*/
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typedef union {
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struct {
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/** status_w1tc : WT; bitpos: [29:0]; default: 0;
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* GPIO interrupt status clear register for GPIO0-29
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*/
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uint32_t status_w1tc:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_status_w1tc_reg_t;
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/** Type of pin register
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* GPIO pin configuration register
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*/
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typedef union {
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struct {
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/** pin_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
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* set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
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* posedge.
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*/
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uint32_t pin_sync2_bypass:2;
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/** pin_pad_driver : R/W; bitpos: [2]; default: 0;
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* set this bit to select pad driver. 1:open-drain. 0:normal.
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*/
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uint32_t pin_pad_driver:1;
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/** pin_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
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* set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
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* posedge.
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*/
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uint32_t pin_sync1_bypass:2;
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uint32_t reserved_5:2;
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/** pin_int_type : R/W; bitpos: [9:7]; default: 0;
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* set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
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* posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
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* at high level
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*/
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uint32_t pin_int_type:3;
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/** pin_wakeup_enable : R/W; bitpos: [10]; default: 0;
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* set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
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*/
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uint32_t pin_wakeup_enable:1;
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/** pin_config : R/W; bitpos: [12:11]; default: 0;
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* reserved
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*/
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uint32_t pin_config:2;
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/** pin_int_ena : R/W; bitpos: [17:13]; default: 0;
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* set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
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* interrupt.
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*/
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uint32_t pin_int_ena:5;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} gpio_pin_reg_t;
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/** Type of status_next register
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* GPIO interrupt source register for GPIO0-29
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*/
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typedef union {
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struct {
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/** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
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* GPIO interrupt source register for GPIO0-29
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*/
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uint32_t status_interrupt_next:32;
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};
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uint32_t val;
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} gpio_status_next_reg_t;
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/** Type of func_in_sel_cfg register
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* GPIO input function configuration register
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*/
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typedef union {
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struct {
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/** func_in_sel : R/W; bitpos: [4:0]; default: 0;
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* set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always
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* high level. s=0x3C: set this port always low level.
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*/
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uint32_t func_in_sel:5;
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/** func_in_inv_sel : R/W; bitpos: [5]; default: 0;
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* set this bit to invert input signal. 1:invert. 0:not invert.
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*/
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uint32_t func_in_inv_sel:1;
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/** sig_in_sel : R/W; bitpos: [6]; default: 0;
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* set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
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*/
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uint32_t sig_in_sel:1;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} gpio_func_in_sel_cfg_reg_t;
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/** Type of func_out_sel_cfg register
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* GPIO output function select register
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*/
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typedef union {
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struct {
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/** func_out_sel : R/W; bitpos: [7:0]; default: 128;
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* The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127:
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* output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
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* GPIO_OUT_REG[n].
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*/
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uint32_t func_out_sel:8;
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/** func_out_inv_sel : R/W; bitpos: [8]; default: 0;
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* set this bit to invert output signal.1:invert.0:not invert.
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*/
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uint32_t func_out_inv_sel:1;
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/** func_oen_sel : R/W; bitpos: [9]; default: 0;
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* set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
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* enable signal.0:use peripheral output enable signal.
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*/
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uint32_t func_oen_sel:1;
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/** func_oen_inv_sel : R/W; bitpos: [10]; default: 0;
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* set this bit to invert output enable signal.1:invert.0:not invert.
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*/
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uint32_t func_oen_inv_sel:1;
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uint32_t reserved_11:21;
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};
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uint32_t val;
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} gpio_func_out_sel_cfg_reg_t;
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/** Type of clock_gate register
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* GPIO clock gate register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 1;
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* set this bit to enable GPIO clock gate
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gpio_clock_gate_reg_t;
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/** Type of reg_date register
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* GPIO version register
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*/
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typedef union {
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struct {
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/** reg_date : R/W; bitpos: [27:0]; default: 34640016;
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* version register
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*/
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uint32_t reg_date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} gpio_reg_date_reg_t;
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/** Group: interrupt register */
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/** Type of pcpu_int register
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* GPIO PRO_CPU interrupt status register for GPIO0-29
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*/
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typedef union {
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struct {
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/** procpu_int : RO; bitpos: [29:0]; default: 0;
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* GPIO PRO_CPU interrupt status register for GPIO0-29
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*/
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uint32_t procpu_int:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_pcpu_int_reg_t;
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/** Type of pcpu_nmi_int register
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* GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29
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*/
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typedef union {
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struct {
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/** procpu_nmi_int : RO; bitpos: [29:0]; default: 0;
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* GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29
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*/
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uint32_t procpu_nmi_int:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_pcpu_nmi_int_reg_t;
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/** Type of cpusdio_int register
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* GPIO CPUSDIO interrupt status register for GPIO0-29
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*/
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typedef union {
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struct {
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/** sdio_int : RO; bitpos: [29:0]; default: 0;
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* GPIO CPUSDIO interrupt status register for GPIO0-29
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*/
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uint32_t sdio_int:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_cpusdio_int_reg_t;
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typedef struct {
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volatile gpio_bt_select_reg_t bt_select;
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volatile gpio_out_reg_t out;
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volatile gpio_out_w1ts_reg_t out_w1ts;
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volatile gpio_out_w1tc_reg_t out_w1tc;
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uint32_t reserved_010[3];
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volatile gpio_sdio_select_reg_t sdio_select;
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volatile gpio_enable_reg_t enable;
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volatile gpio_enable_w1ts_reg_t enable_w1ts;
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volatile gpio_enable_w1tc_reg_t enable_w1tc;
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uint32_t reserved_02c[3];
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volatile gpio_strap_reg_t strap;
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volatile gpio_in_reg_t in;
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uint32_t reserved_040;
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volatile gpio_status_reg_t status;
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volatile gpio_status_w1ts_reg_t status_w1ts;
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volatile gpio_status_w1tc_reg_t status_w1tc;
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uint32_t reserved_050[3];
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volatile gpio_pcpu_int_reg_t pcpu_int;
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volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int;
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volatile gpio_cpusdio_int_reg_t cpusdio_int;
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uint32_t reserved_068[3];
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volatile gpio_pin_reg_t pin[30];
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uint32_t reserved_0ec[24];
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volatile gpio_status_next_reg_t status_next;
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uint32_t reserved_150;
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volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128];
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uint32_t reserved_354[128];
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volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[30];
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uint32_t reserved_5cc[24];
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volatile gpio_clock_gate_reg_t clock_gate;
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uint32_t reserved_630[51];
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volatile gpio_reg_date_reg_t reg_date;
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} gpio_dev_t;
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extern gpio_dev_t GPIO;
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#ifndef __cplusplus
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_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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