mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-20 10:46:02 -04:00
a9fda54d39
This commit updates the visibility of various header files and cleans up some unnecessary inclusions. Also, this commit removes certain header include paths which were maintained for backward compatibility.
151 lines
4.2 KiB
C
151 lines
4.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/efuse_periph.h"
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#include "rtc_wdt.h"
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#include "soc/rtc.h"
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#include "hal/efuse_ll.h"
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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bool rtc_wdt_get_protect_status(void)
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{
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return READ_PERI_REG(RTC_CNTL_WDTWPROTECT_REG) != RTC_CNTL_WDT_WKEY_VALUE;
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}
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void rtc_wdt_protect_off(void)
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{
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WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
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}
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void rtc_wdt_protect_on(void)
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{
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WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
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}
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void rtc_wdt_enable(void)
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{
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REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED);
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SET_PERI_REG_MASK(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN | RTC_CNTL_WDT_PAUSE_IN_SLP);
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}
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void rtc_wdt_flashboot_mode_enable(void)
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{
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REG_SET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
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}
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void rtc_wdt_disable(void)
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{
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bool protect = rtc_wdt_get_protect_status();
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if (protect) {
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rtc_wdt_protect_off();
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}
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REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED);
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rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_OFF);
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rtc_wdt_set_stage(RTC_WDT_STAGE1, RTC_WDT_STAGE_ACTION_OFF);
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rtc_wdt_set_stage(RTC_WDT_STAGE2, RTC_WDT_STAGE_ACTION_OFF);
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rtc_wdt_set_stage(RTC_WDT_STAGE3, RTC_WDT_STAGE_ACTION_OFF);
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REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
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REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN);
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if (protect) {
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rtc_wdt_protect_on();
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}
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}
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void rtc_wdt_feed(void)
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{
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bool protect = rtc_wdt_get_protect_status();
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if (protect) {
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rtc_wdt_protect_off();
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}
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REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED);
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if (protect) {
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rtc_wdt_protect_on();
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}
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}
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static uint32_t get_addr_reg(rtc_wdt_stage_t stage)
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{
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uint32_t reg;
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if (stage == RTC_WDT_STAGE0) {
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reg = RTC_CNTL_WDTCONFIG1_REG;
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} else if (stage == RTC_WDT_STAGE1) {
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reg = RTC_CNTL_WDTCONFIG2_REG;
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} else if (stage == RTC_WDT_STAGE2) {
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reg = RTC_CNTL_WDTCONFIG3_REG;
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} else {
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reg = RTC_CNTL_WDTCONFIG4_REG;
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}
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return reg;
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}
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esp_err_t rtc_wdt_set_time(rtc_wdt_stage_t stage, unsigned int timeout_ms)
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{
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if (stage > 3) {
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return ESP_ERR_INVALID_ARG;
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}
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uint32_t timeout = (uint32_t) ((uint64_t) rtc_clk_slow_freq_get_hz() * timeout_ms / 1000);
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#if !CONFIG_IDF_TARGET_ESP32
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if (stage == RTC_WDT_STAGE0) {
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timeout = timeout >> (1 + efuse_ll_get_wdt_delay_sel());
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}
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#endif
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WRITE_PERI_REG(get_addr_reg(stage), timeout);
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return ESP_OK;
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}
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esp_err_t rtc_wdt_get_timeout(rtc_wdt_stage_t stage, unsigned int* timeout_ms)
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{
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if (stage > 3) {
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return ESP_ERR_INVALID_ARG;
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}
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uint32_t time_tick;
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time_tick = READ_PERI_REG(get_addr_reg(stage));
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*timeout_ms = time_tick * 1000 / rtc_clk_slow_freq_get_hz();
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return ESP_OK;
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}
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esp_err_t rtc_wdt_set_stage(rtc_wdt_stage_t stage, rtc_wdt_stage_action_t stage_sel)
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{
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if (stage > 3 || stage_sel > 4) {
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return ESP_ERR_INVALID_ARG;
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}
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if (stage == RTC_WDT_STAGE0) {
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG0, stage_sel);
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} else if (stage == RTC_WDT_STAGE1) {
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG1, stage_sel);
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} else if (stage == RTC_WDT_STAGE2) {
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG2, stage_sel);
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} else {
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG3, stage_sel);
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}
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return ESP_OK;
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}
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esp_err_t rtc_wdt_set_length_of_reset_signal(rtc_wdt_reset_sig_t reset_src, rtc_wdt_length_sig_t reset_signal_length)
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{
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if (reset_src > 1 || reset_signal_length > 7) {
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return ESP_ERR_INVALID_ARG;
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}
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if (reset_src == 0) {
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_SYS_RESET_LENGTH, reset_signal_length);
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} else {
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_CPU_RESET_LENGTH, reset_signal_length);
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}
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return ESP_OK;
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}
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bool rtc_wdt_is_on(void)
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{
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return (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN) != 0) || (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN) != 0);
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}
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#endif // CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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