mirror of
https://github.com/espressif/esp-idf.git
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64 lines
3.5 KiB
C
64 lines
3.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DR_REG_SYSTEM_BASE 0x3f4c0000
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#define DR_REG_SENSITIVE_BASE 0x3f4c1000
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#define DR_REG_INTERRUPT_BASE 0x3f4c2000
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#define DR_REG_DMA_COPY_BASE 0x3f4c3000
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#define DR_REG_EXTMEM_BASE 0x61800000
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#define DR_REG_MMU_TABLE 0x61801000
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#define DR_REG_ITAG_TABLE 0x61802000
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#define DR_REG_DTAG_TABLE 0x61803000
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#define DR_REG_AES_BASE 0x6003a000
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#define DR_REG_SHA_BASE 0x6003b000
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#define DR_REG_RSA_BASE 0x6003c000
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#define DR_REG_HMAC_BASE 0x6003e000
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#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
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#define DR_REG_CRYPTO_DMA_BASE 0x6003f000
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#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
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#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
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#define DR_REG_INTRUSION_BASE 0x3f4d0000
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#define DR_REG_DPORT_END 0x3f4d3FFC
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#define DR_REG_UART_BASE 0x3f400000
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#define DR_REG_SPI1_BASE 0x3f402000
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#define DR_REG_SPI0_BASE 0x3f403000
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#define DR_REG_GPIO_BASE 0x3f404000
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#define DR_REG_GPIO_SD_BASE 0x3f404f00
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#define DR_REG_FE2_BASE 0x3f405000
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#define DR_REG_FE_BASE 0x3f406000
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#define DR_REG_FRC_TIMER_BASE 0x3f407000
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#define DR_REG_RTCCNTL_BASE 0x3f408000
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#define DR_REG_RTCIO_BASE 0x3f408400
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#define DR_REG_SENS_BASE 0x3f408800
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#define DR_REG_RTC_I2C_BASE 0x3f408C00
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#define DR_REG_IO_MUX_BASE 0x3f409000
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#define DR_REG_HINF_BASE 0x3f40B000
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#define DR_REG_I2S_BASE 0x3f40F000
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#define DR_REG_UART1_BASE 0x3f410000
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#define DR_REG_I2C_EXT_BASE 0x3f413000
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#define DR_REG_UHCI0_BASE 0x3f414000
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#define DR_REG_SLCHOST_BASE 0x3f415000
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#define DR_REG_RMT_BASE 0x3f416000
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#define DR_REG_PCNT_BASE 0x3f417000
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#define DR_REG_SLC_BASE 0x3f418000
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#define DR_REG_LEDC_BASE 0x3f419000
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#define DR_REG_CP_BASE 0x3f4c3000
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#define DR_REG_EFUSE_BASE 0x3f41A000
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#define DR_REG_NRX_BASE 0x3f41CC00
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#define DR_REG_BB_BASE 0x3f41D000
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#define DR_REG_TIMERGROUP0_BASE 0x3f41F000
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#define DR_REG_TIMERGROUP1_BASE 0x3f420000
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#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000
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#define DR_REG_SYSTIMER_BASE 0x3f423000
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#define DR_REG_SPI2_BASE 0x3f424000
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#define DR_REG_SPI3_BASE 0x3f425000
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#define DR_REG_SYSCON_BASE 0x3f426000
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#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */
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#define DR_REG_I2C1_EXT_BASE 0x3f427000
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#define DR_REG_SPI4_BASE 0x3f437000
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#define DR_REG_USB_WRAP_BASE 0x3f439000
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#define DR_REG_APB_SARADC_BASE 0x3f440000
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#define DR_REG_USB_BASE 0x60080000
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