mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
824c8e0593
This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:
- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data
If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):
.dram0.bss (NOLOAD) :
{
arrays[dram0_bss]
mapping[dram0_bss]
} > sram_low
.dram1.bss (NOLOAD) :
{
/* do not place here arrays[dram0_bss] because it may be splited
* between segments */
mapping[dram0_bss]
} > sram_high
57 lines
2.0 KiB
Plaintext
57 lines
2.0 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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/* CPU instruction prefetch padding size for flash mmap scenario */
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#define _esp_flash_mmap_prefetch_pad_size 16
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/* CPU instruction prefetch padding size for memory protection scenario */
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#ifdef CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
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#define _esp_memprot_prefetch_pad_size CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
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#else
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#define _esp_memprot_prefetch_pad_size 0
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#endif
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/* Memory alignment size for PMS */
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#ifdef CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE
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#define _esp_memprot_align_size CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE
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#else
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#define _esp_memprot_align_size 0
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#endif
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#if CONFIG_APP_BUILD_TYPE_RAM
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#define _esp_mmu_block_size 0
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#else
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#define _esp_mmu_block_size CONFIG_MMU_PAGE_SIZE
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#endif
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#if CONFIG_SOC_RTC_MEM_SUPPORTED
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#if CONFIG_BOOTLOADER_RESERVE_RTC_MEM
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#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
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#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
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#else
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#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
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#endif // not CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
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#else
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#define ESP_BOOTLOADER_RESERVE_RTC 0
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#endif // not CONFIG_BOOTLOADER_RESERVE_RTC_MEM
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/* rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). For rtc_timer_data_in_rtc_mem section. */
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#define RTC_TIMER_RESERVE_RTC (24)
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#if CONFIG_IDF_TARGET_ESP32
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#define RESERVE_RTC_MEM (RTC_TIMER_RESERVE_RTC)
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#else
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#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC)
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#endif
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#endif // SOC_RTC_MEM_SUPPORTED
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#define QUOTED_STRING(STRING) #STRING
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#define ASSERT_SECTIONS_GAP(PREV_SECTION, NEXT_SECTION) \
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ASSERT((ADDR(NEXT_SECTION) == ADDR(PREV_SECTION) + SIZEOF(PREV_SECTION)), \
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QUOTED_STRING(The gap between PREV_SECTION and NEXT_SECTION must not exist to produce the final bin image.))
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