mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
c8c65a2854
* Adds implementations of __{atomic,sync}_nand_fetch_n. These builtins
were implemented for other operations but were not defined for NAND.
* Adds implementation of __atomic_OP_fetch_n for all OPs.
* Adds implementation of __sync_OP_and_fetch_n for all OPs.
Reported in https://github.com/espressif/arduino-esp32/issues/5948
491 lines
15 KiB
C
491 lines
15 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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//replacement for gcc built-in functions
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#include "sdkconfig.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "freertos/FreeRTOS.h"
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#ifdef __XTENSA__
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#include "xtensa/config/core-isa.h"
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#ifndef XCHAL_HAVE_S32C1I
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#error "XCHAL_HAVE_S32C1I not defined, include correct header!"
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#endif
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#define HAS_ATOMICS_32 (XCHAL_HAVE_S32C1I == 1)
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// no 64-bit atomics on Xtensa
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#define HAS_ATOMICS_64 0
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#else // RISCV
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// GCC toolchain will define this pre-processor if "A" extension is supported
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#ifndef __riscv_atomic
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#define __riscv_atomic 0
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#endif
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#define HAS_ATOMICS_32 (__riscv_atomic == 1)
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#define HAS_ATOMICS_64 ((__riscv_atomic == 1) && (__riscv_xlen == 64))
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#endif // (__XTENSA__, __riscv)
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#if SOC_CPU_CORES_NUM == 1
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// Single core SoC: atomics can be implemented using portSET_INTERRUPT_MASK_FROM_ISR
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// and portCLEAR_INTERRUPT_MASK_FROM_ISR, which disables and enables interrupts.
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#define _ATOMIC_ENTER_CRITICAL() ({ \
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unsigned state = portSET_INTERRUPT_MASK_FROM_ISR(); \
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state; \
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})
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#define _ATOMIC_EXIT_CRITICAL(state) do { \
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portCLEAR_INTERRUPT_MASK_FROM_ISR(state); \
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} while (0)
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#else // SOC_CPU_CORES_NUM
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_Static_assert(HAS_ATOMICS_32, "32-bit atomics should be supported if SOC_CPU_CORES_NUM > 1");
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// Only need to implement 64-bit atomics here. Use a single global portMUX_TYPE spinlock
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// to emulate the atomics.
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static portMUX_TYPE s_atomic_lock = portMUX_INITIALIZER_UNLOCKED;
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// Return value is not used but kept for compatibility with the single-core version above.
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#define _ATOMIC_ENTER_CRITICAL() ({ \
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portENTER_CRITICAL_SAFE(&s_atomic_lock); \
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0; \
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})
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#define _ATOMIC_EXIT_CRITICAL(state) do { \
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(void) (state); \
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portEXIT_CRITICAL_SAFE(&s_atomic_lock); \
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} while(0)
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#endif // SOC_CPU_CORES_NUM
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#ifdef __clang__
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// Clang doesn't allow to define "__sync_*" atomics. The workaround is to define function with name "__sync_*_builtin",
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// which implements "__sync_*" atomic functionality and use asm directive to set the value of symbol "__sync_*" to the name
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// of defined function.
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#define CLANG_ATOMIC_SUFFIX(name_) name_ ## _builtin
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#define CLANG_DECLARE_ALIAS(name_) \
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__asm__(".type " # name_ ", @function\n" \
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".global " #name_ "\n" \
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".equ " #name_ ", " #name_ "_builtin");
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#else // __clang__
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#define CLANG_ATOMIC_SUFFIX(name_) name_
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#define CLANG_DECLARE_ALIAS(name_)
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#endif // __clang__
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#define ATOMIC_LOAD(n, type) type __atomic_load_ ## n (const type* mem, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *mem; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define ATOMIC_STORE(n, type) void __atomic_store_ ## n (type* mem, type val, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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*mem = val; \
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_ATOMIC_EXIT_CRITICAL(state); \
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}
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#define ATOMIC_EXCHANGE(n, type) type __atomic_exchange_ ## n (type* mem, type val, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *mem; \
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*mem = val; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define CMP_EXCHANGE(n, type) bool __atomic_compare_exchange_ ## n (type* mem, type* expect, type desired, bool weak, int success, int failure) \
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{ \
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bool ret = false; \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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if (*mem == *expect) { \
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ret = true; \
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*mem = desired; \
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} else { \
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*expect = *mem; \
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} \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_ADD(n, type) type __atomic_fetch_add_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr + value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define ADD_FETCH(n, type) type __atomic_add_fetch_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr + value; \
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*ptr = ret; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_SUB(n, type) type __atomic_fetch_sub_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr - value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define SUB_FETCH(n, type) type __atomic_sub_fetch_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr - value; \
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*ptr = ret; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_AND(n, type) type __atomic_fetch_and_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr & value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define AND_FETCH(n, type) type __atomic_and_fetch_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr & value; \
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*ptr = ret; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_OR(n, type) type __atomic_fetch_or_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr | value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define OR_FETCH(n, type) type __atomic_or_fetch_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr | value; \
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*ptr = ret; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_XOR(n, type) type __atomic_fetch_xor_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr ^ value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define XOR_FETCH(n, type) type __atomic_xor_fetch_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr ^ value; \
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*ptr = ret; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_NAND(n, type) type __atomic_fetch_nand_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = ~(*ptr & value); \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define NAND_FETCH(n, type) type __atomic_nand_fetch_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = ~(*ptr & value); \
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*ptr = ret; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define SYNC_FETCH_OP(op, n, type) type CLANG_ATOMIC_SUFFIX(__sync_fetch_and_ ## op ##_ ## n) (type* ptr, type value) \
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{ \
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return __atomic_fetch_ ## op ##_ ## n (ptr, value, __ATOMIC_SEQ_CST); \
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} \
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CLANG_DECLARE_ALIAS( __sync_fetch_and_ ## op ##_ ## n )
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#define SYNC_OP_FETCH(op, n, type) type CLANG_ATOMIC_SUFFIX(__sync_ ## op ##_and_fetch_ ## n) (type* ptr, type value) \
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{ \
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return __atomic_ ## op ##_fetch_ ## n (ptr, value, __ATOMIC_SEQ_CST); \
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} \
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CLANG_DECLARE_ALIAS( __sync_ ## op ##_and_fetch_ ## n )
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#define SYNC_BOOL_CMP_EXCHANGE(n, type) bool CLANG_ATOMIC_SUFFIX(__sync_bool_compare_and_swap_ ## n) (type *ptr, type oldval, type newval) \
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{ \
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bool ret = false; \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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if (*ptr == oldval) { \
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*ptr = newval; \
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ret = true; \
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} \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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} \
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CLANG_DECLARE_ALIAS( __sync_bool_compare_and_swap_ ## n )
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#define SYNC_VAL_CMP_EXCHANGE(n, type) type CLANG_ATOMIC_SUFFIX(__sync_val_compare_and_swap_ ## n) (type *ptr, type oldval, type newval) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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if (*ptr == oldval) { \
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*ptr = newval; \
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} \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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} \
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CLANG_DECLARE_ALIAS( __sync_val_compare_and_swap_ ## n )
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#define SYNC_LOCK_TEST_AND_SET(n, type) type CLANG_ATOMIC_SUFFIX(__sync_lock_test_and_set_ ## n) (type *ptr, type val) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = val; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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} \
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CLANG_DECLARE_ALIAS( __sync_lock_test_and_set_ ## n )
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#define SYNC_LOCK_RELEASE(n, type) void CLANG_ATOMIC_SUFFIX(__sync_lock_release_ ## n) (type *ptr) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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*ptr = 0; \
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_ATOMIC_EXIT_CRITICAL(state); \
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} \
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CLANG_DECLARE_ALIAS( __sync_lock_release_ ## n )
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#if !HAS_ATOMICS_32
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ATOMIC_EXCHANGE(1, uint8_t)
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ATOMIC_EXCHANGE(2, uint16_t)
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ATOMIC_EXCHANGE(4, uint32_t)
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CMP_EXCHANGE(1, uint8_t)
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CMP_EXCHANGE(2, uint16_t)
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CMP_EXCHANGE(4, uint32_t)
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FETCH_ADD(1, uint8_t)
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FETCH_ADD(2, uint16_t)
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FETCH_ADD(4, uint32_t)
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ADD_FETCH(1, uint8_t)
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ADD_FETCH(2, uint16_t)
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ADD_FETCH(4, uint32_t)
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FETCH_SUB(1, uint8_t)
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FETCH_SUB(2, uint16_t)
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FETCH_SUB(4, uint32_t)
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SUB_FETCH(1, uint8_t)
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SUB_FETCH(2, uint16_t)
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SUB_FETCH(4, uint32_t)
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FETCH_AND(1, uint8_t)
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FETCH_AND(2, uint16_t)
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FETCH_AND(4, uint32_t)
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AND_FETCH(1, uint8_t)
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AND_FETCH(2, uint16_t)
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AND_FETCH(4, uint32_t)
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FETCH_OR(1, uint8_t)
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FETCH_OR(2, uint16_t)
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FETCH_OR(4, uint32_t)
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OR_FETCH(1, uint8_t)
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OR_FETCH(2, uint16_t)
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OR_FETCH(4, uint32_t)
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FETCH_XOR(1, uint8_t)
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FETCH_XOR(2, uint16_t)
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FETCH_XOR(4, uint32_t)
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XOR_FETCH(1, uint8_t)
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XOR_FETCH(2, uint16_t)
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XOR_FETCH(4, uint32_t)
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FETCH_NAND(1, uint8_t)
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FETCH_NAND(2, uint16_t)
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FETCH_NAND(4, uint32_t)
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NAND_FETCH(1, uint8_t)
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NAND_FETCH(2, uint16_t)
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NAND_FETCH(4, uint32_t)
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SYNC_FETCH_OP(add, 1, uint8_t)
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SYNC_FETCH_OP(add, 2, uint16_t)
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SYNC_FETCH_OP(add, 4, uint32_t)
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SYNC_OP_FETCH(add, 1, uint8_t)
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SYNC_OP_FETCH(add, 2, uint16_t)
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SYNC_OP_FETCH(add, 4, uint32_t)
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SYNC_FETCH_OP(sub, 1, uint8_t)
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SYNC_FETCH_OP(sub, 2, uint16_t)
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SYNC_FETCH_OP(sub, 4, uint32_t)
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SYNC_OP_FETCH(sub, 1, uint8_t)
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SYNC_OP_FETCH(sub, 2, uint16_t)
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SYNC_OP_FETCH(sub, 4, uint32_t)
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SYNC_FETCH_OP(and, 1, uint8_t)
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SYNC_FETCH_OP(and, 2, uint16_t)
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SYNC_FETCH_OP(and, 4, uint32_t)
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SYNC_OP_FETCH(and, 1, uint8_t)
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SYNC_OP_FETCH(and, 2, uint16_t)
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SYNC_OP_FETCH(and, 4, uint32_t)
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SYNC_FETCH_OP(or, 1, uint8_t)
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SYNC_FETCH_OP(or, 2, uint16_t)
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SYNC_FETCH_OP(or, 4, uint32_t)
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SYNC_OP_FETCH(or, 1, uint8_t)
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SYNC_OP_FETCH(or, 2, uint16_t)
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SYNC_OP_FETCH(or, 4, uint32_t)
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SYNC_FETCH_OP(xor, 1, uint8_t)
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SYNC_FETCH_OP(xor, 2, uint16_t)
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SYNC_FETCH_OP(xor, 4, uint32_t)
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SYNC_OP_FETCH(xor, 1, uint8_t)
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SYNC_OP_FETCH(xor, 2, uint16_t)
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SYNC_OP_FETCH(xor, 4, uint32_t)
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SYNC_FETCH_OP(nand, 1, uint8_t)
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SYNC_FETCH_OP(nand, 2, uint16_t)
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SYNC_FETCH_OP(nand, 4, uint32_t)
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SYNC_OP_FETCH(nand, 1, uint8_t)
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SYNC_OP_FETCH(nand, 2, uint16_t)
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SYNC_OP_FETCH(nand, 4, uint32_t)
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SYNC_BOOL_CMP_EXCHANGE(1, uint8_t)
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SYNC_BOOL_CMP_EXCHANGE(2, uint16_t)
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SYNC_BOOL_CMP_EXCHANGE(4, uint32_t)
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SYNC_VAL_CMP_EXCHANGE(1, uint8_t)
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SYNC_VAL_CMP_EXCHANGE(2, uint16_t)
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SYNC_VAL_CMP_EXCHANGE(4, uint32_t)
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SYNC_LOCK_TEST_AND_SET(1, uint8_t)
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SYNC_LOCK_TEST_AND_SET(2, uint16_t)
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SYNC_LOCK_TEST_AND_SET(4, uint32_t)
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SYNC_LOCK_RELEASE(1, uint8_t)
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SYNC_LOCK_RELEASE(2, uint16_t)
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SYNC_LOCK_RELEASE(4, uint32_t)
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// LLVM has not implemented native atomic load/stores for riscv targets without the Atomic extension. LLVM thread: https://reviews.llvm.org/D47553.
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// Even though GCC does transform them, these libcalls need to be available for the case where a LLVM based project links against IDF.
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ATOMIC_LOAD(1, uint8_t)
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ATOMIC_LOAD(2, uint16_t)
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ATOMIC_LOAD(4, uint32_t)
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ATOMIC_STORE(1, uint8_t)
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ATOMIC_STORE(2, uint16_t)
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ATOMIC_STORE(4, uint32_t)
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#endif // !HAS_ATOMICS_32
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#if !HAS_ATOMICS_64
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ATOMIC_EXCHANGE(8, uint64_t)
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CMP_EXCHANGE(8, uint64_t)
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FETCH_ADD(8, uint64_t)
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FETCH_SUB(8, uint64_t)
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FETCH_AND(8, uint64_t)
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FETCH_OR(8, uint64_t)
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FETCH_XOR(8, uint64_t)
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FETCH_NAND(8, uint64_t)
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ADD_FETCH(8, uint64_t)
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SUB_FETCH(8, uint64_t)
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AND_FETCH(8, uint64_t)
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OR_FETCH(8, uint64_t)
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XOR_FETCH(8, uint64_t)
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NAND_FETCH(8, uint64_t)
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SYNC_FETCH_OP(add, 8, uint64_t)
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SYNC_FETCH_OP(sub, 8, uint64_t)
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SYNC_FETCH_OP(and, 8, uint64_t)
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SYNC_FETCH_OP(or, 8, uint64_t)
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SYNC_FETCH_OP(xor, 8, uint64_t)
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SYNC_FETCH_OP(nand, 8, uint64_t)
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SYNC_OP_FETCH(add, 8, uint64_t)
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SYNC_OP_FETCH(sub, 8, uint64_t)
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SYNC_OP_FETCH(and, 8, uint64_t)
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SYNC_OP_FETCH(or, 8, uint64_t)
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SYNC_OP_FETCH(xor, 8, uint64_t)
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SYNC_OP_FETCH(nand, 8, uint64_t)
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SYNC_BOOL_CMP_EXCHANGE(8, uint64_t)
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SYNC_VAL_CMP_EXCHANGE(8, uint64_t)
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SYNC_LOCK_TEST_AND_SET(8, uint64_t)
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SYNC_LOCK_RELEASE(8, uint64_t)
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// LLVM has not implemented native atomic load/stores for riscv targets without the Atomic extension. LLVM thread: https://reviews.llvm.org/D47553.
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// Even though GCC does transform them, these libcalls need to be available for the case where a LLVM based project links against IDF.
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ATOMIC_LOAD(8, uint64_t)
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ATOMIC_STORE(8, uint64_t)
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#endif // !HAS_ATOMICS_64
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