mirror of
https://github.com/espressif/esp-idf.git
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242 lines
8.8 KiB
C
242 lines
8.8 KiB
C
/* Copyright (c) 2002-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
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/ These coded instructions, statements, and computer programs are the
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/ copyrighted works and confidential proprietary information of Tensilica Inc.
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/ They may not be modified, copied, reproduced, distributed, or disclosed to
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/ third parties in any manner, medium, or form, in whole or in part, without
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/ the prior written consent of Tensilica Inc.
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*/
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/* xtav60.h - Xtensa Avnet LX60 (XT-AV60) board specific definitions */
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#ifndef _INC_XTAV60_H_
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#define _INC_XTAV60_H_
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#include <xtensa/config/core.h>
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#include <xtensa/config/system.h>
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#define XTBOARD_NAME "XT-AV60"
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/*
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* Default assignment of XTAV60 devices to external interrupts.
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*/
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/* Ethernet interrupt: */
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#ifdef XCHAL_EXTINT1_NUM
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#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM
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#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL
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#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK
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#else
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#define ETHERNET_INTMASK 0
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#endif
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/* UART interrupt: */
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#ifdef XCHAL_EXTINT0_NUM
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#define UART16550_INTNUM XCHAL_EXTINT0_NUM
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#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL
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#define UART16550_INTMASK XCHAL_EXTINT0_MASK
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#else
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#define UART16550_INTMASK 0
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#endif
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/*
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* Device addresses.
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*
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* Note: for endianness-independence, use 32-bit loads and stores for all
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* register accesses to Ethernet, UART and LED devices. Undefined bits
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* may need to be masked out if needed when reading if the actual register
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* size is smaller than 32 bits.
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*
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* Note: XTAV60 bus byte lanes are defined in terms of msbyte and lsbyte
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* relative to the processor. So 32-bit registers are accessed consistently
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* from both big and little endian processors. However, this means byte
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* sequences are not consistent between big and little endian processors.
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* This is fine for RAM, and for ROM if ROM is created for a specific
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* processor (and thus has correct byte sequences). However this may be
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* unexpected for Flash, which might contain a file-system that one wants
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* to use for multiple processor configurations (eg. the Flash might contain
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* the Ethernet card's address, endianness-independent application data, etc).
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* That is, byte sequences written in Flash by a core of a given endianness
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* will be byte-swapped when seen by a core of the other endianness.
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* Someone implementing an endianness-independent Flash file system will
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* likely handle this byte-swapping issue in the Flash driver software.
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*/
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#define XTBOARD_FLASH_MAXSIZE 0x400000 /* 4 MB */
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#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
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/* Flash Memory: */
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# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000)
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/* FPGA registers: */
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# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000)
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/* Ethernet controller/transceiver SONIC SN83934: */
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# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000)
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# define ETHERNET_CONTROLLER_PADDR ETHERNET_PADDR /* legacy macro */
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/* Display controller Sunplus SPLC780D, LCD Display MYTech MOC-16216B-B: */
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# define SPLC780D_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D040000)
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/* UART National-Semi PC16550D: */
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# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000)
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/* Boot 128K Sram address: */
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# define BOOT_SRAM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D400000)
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/* Ethernet buffer: */
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# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000)
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#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
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/* These devices might be accessed cached: */
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#ifdef XSHAL_IOBLOCK_CACHED_PADDR
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# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000)
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# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000)
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# define BOOT_SRAM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D400000)
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#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
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/*** Same thing over again, this time with virtual addresses: ***/
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#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
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/* Flash Memory: */
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# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000)
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/* FPGA registers: */
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# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000)
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/* Ethernet controller/transceiver SONIC SN83934: */
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# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000)
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/* Display controller Sunplus SPLC780D, LCD Display MYTech MOC-16216B-B: */
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# define SPLC780D_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D040000)
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/* UART National-Semi PC16550D: */
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# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000)
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/* 128K Sram address: */
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# define BOOT_SRAM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D400000)
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/* Ethernet buffer: */
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# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000)
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#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
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/* These devices might be accessed cached: */
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#ifdef XSHAL_IOBLOCK_CACHED_VADDR
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# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000)
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# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000)
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# define BOOT_SRAM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D400000)
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#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
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/* System ROM: */
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#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
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#ifdef XSHAL_ROM_VADDR
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#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
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#endif
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#ifdef XSHAL_ROM_PADDR
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#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
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#endif
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/* System RAM: */
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#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
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#ifdef XSHAL_RAM_VADDR
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#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
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#endif
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#ifdef XSHAL_RAM_PADDR
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#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
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#endif
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#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
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#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
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/*
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* Things that depend on device addresses.
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*/
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#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
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#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
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#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
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#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
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#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
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#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
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#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
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/*
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* FPGA registers.
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* All these registers are normally accessed using 32-bit loads/stores.
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*/
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/* Register offsets: */
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#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */
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#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */
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#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */
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#define XTBOARD_SWRST_OFS 0x10 /* software reset */
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/* Physical register addresses: */
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#ifdef XTBOARD_FPGAREGS_PADDR
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#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS)
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#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS)
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#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS)
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#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS)
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#endif
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/* Virtual register addresses: */
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#ifdef XTBOARD_FPGAREGS_VADDR
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#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS)
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#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS)
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#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS)
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#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS)
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/* Register access (for C code): */
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#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR)
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#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR)
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#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR)
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#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR)
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#endif
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/* DATECD (date code; when core was built) bit fields: */
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/* BCD-coded month (01..12): */
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#define XTBOARD_DATECD_MONTH_SHIFT 24
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#define XTBOARD_DATECD_MONTH_BITS 8
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#define XTBOARD_DATECD_MONTH_MASK 0xFF000000
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/* BCD-coded day (01..31): */
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#define XTBOARD_DATECD_DAY_SHIFT 16
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#define XTBOARD_DATECD_DAY_BITS 8
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#define XTBOARD_DATECD_DAY_MASK 0x00FF0000
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/* BCD-coded year (2001..9999): */
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#define XTBOARD_DATECD_YEAR_SHIFT 0
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#define XTBOARD_DATECD_YEAR_BITS 16
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#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF
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/* DIP Switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): */
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/* DIP switch bit fields (bit6/sw7 is reserved and presently unused): */
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#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-6 (1=lsb) */
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#define XTBOARD_DIPSW_USER_BITS 6
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#define XTBOARD_DIPSW_USER_MASK 0x0000003F
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#define XTBOARD_DIPSW_BOOT_SHIFT 7 /* labeled 8 (msb) */
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#define XTBOARD_DIPSW_BOOT_BITS 1
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#define XTBOARD_DIPSW_BOOT_MASK 0x00000080
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/* Boot settings: bit7/sw8, off=0, on=1 (this switch controls hardware): */
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#define XTBOARD_DIPSW_BOOT_RAM (0<<XTBOARD_DIPSW_BOOT_SHIFT) /* off */
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#define XTBOARD_DIPSW_BOOT_FLASH (1<<XTBOARD_DIPSW_BOOT_SHIFT) /* on */
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/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
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/* Software reset bits: */
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#define XTBOARD_SWRST_SWR_SHIFT 0
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#define XTBOARD_SWRST_SWR_BITS 16
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#define XTBOARD_SWRST_SWR_MASK 0x0000FFFF
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/* Software reset value -- writing this value resets the board: */
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#define XTBOARD_SWRST_RESETVALUE 0x0000DEAD
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#endif /*_INC_XTAV60_H_*/
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