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https://github.com/espressif/esp-idf.git
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a3cc43485f
Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA
104 lines
2.9 KiB
C
104 lines
2.9 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The HAL is not public api, don't use in application code.
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* See readme.md in soc/README.md
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******************************************************************************/
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// CP DMA HAL usages:
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// 1. Initialize HAL layer by cp_dma_hal_init, pass in the allocated descriptors for TX and RX
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// 2. Enable DMA and interrupt by cp_dma_hal_start
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// 3. Prepare descriptors used for TX and RX
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// 4. Restart the DMA engine in case it's not in working
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stddef.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "hal/dma_types.h"
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#include "soc/cp_dma_struct.h"
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/**
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* @brief HAL context
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*
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*/
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typedef struct {
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cp_dma_dev_t *dev;
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} cp_dma_hal_context_t;
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typedef struct {
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dma_descriptor_t *outlink_base; /*!< Address of the first outlink descriptor */
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dma_descriptor_t *inlink_base; /*!< Address of the first inlink descriptor */
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} cp_dma_hal_config_t;
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/**
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* @brief Initialize HAL layer context
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*
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* @param hal HAL layer context, whose memroy should be allocated at driver layer
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* @param config configuration for the HAL layer
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*/
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void cp_dma_hal_init(cp_dma_hal_context_t *hal, const cp_dma_hal_config_t *config);
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/**
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* @brief Deinitialize HAL layer context
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*/
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void cp_dma_hal_deinit(cp_dma_hal_context_t *hal);
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/**
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* @brief Start mem2mem DMA state machine
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*/
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void cp_dma_hal_start(cp_dma_hal_context_t *hal);
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/**
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* @brief Stop mem2mem DMA state machine
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*/
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void cp_dma_hal_stop(cp_dma_hal_context_t *hal);
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/**
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* @brief Get interrupt status word
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*
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* @return uint32_t Interrupt status
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*/
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uint32_t cp_dma_hal_get_intr_status(cp_dma_hal_context_t *hal) IRAM_ATTR;
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/**
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* @brief Clear interrupt mask
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*
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* @param mask interrupt mask
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*/
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void cp_dma_hal_clear_intr_status(cp_dma_hal_context_t *hal, uint32_t mask) IRAM_ATTR;
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/**@{*/
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/**
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* @brief Give the owner of descriptors between [start_desc, end_desc] to DMA, and restart DMA HW engine
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*
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* @param hal HAL layer context
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* @param start_desc The first descriptor that carries one transaction
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* @param end_desc The last descriptor that carries one transaction
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*/
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void cp_dma_hal_restart_tx(cp_dma_hal_context_t *hal);
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void cp_dma_hal_restart_rx(cp_dma_hal_context_t *hal);
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/**@}*/
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#ifdef __cplusplus
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}
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#endif
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