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201 lines
8.1 KiB
C
201 lines
8.1 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/apb_ctrl_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/rtc.h"
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#include "soc/i2s_reg.h"
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#include "soc/timer_group_reg.h"
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#include "soc/bb_reg.h"
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#include "soc/nrx_reg.h"
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#include "soc/fe_reg.h"
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#include "soc/rtc.h"
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#include "esp32s2beta/rom/ets_sys.h"
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#define MHZ (1000000)
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/**
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* Configure whether certain peripherals are powered down in deep sleep
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* @param cfg power down flags as rtc_sleep_pd_config_t structure
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*/
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void rtc_sleep_pd(rtc_sleep_pd_config_t cfg)
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{
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REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
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REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
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REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
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//DPORT_REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd);
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REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, cfg.i2s_fpu);
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REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, cfg.i2s_fpu);
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REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
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}
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void rtc_sleep_init(rtc_sleep_config_t cfg)
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{
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/* Already defined in rtc init
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// set 5 PWC state machine times to fit in main state machine time
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, RTC_CNTL_XTL_BUF_WAIT_SLP);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP);
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*/
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/* I don't think it worthes to run this function everytime as it is just a test option */
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if (cfg.lslp_mem_inf_fpu)
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{
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rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(1);
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rtc_sleep_pd(pd_cfg);
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}
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/* This option seems to be unneccessary
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if (cfg.rtc_mem_inf_fpu) {
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
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}
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*/
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if (cfg.rtc_mem_inf_follow_cpu) {
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU);
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}
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if (cfg.rtc_fastmem_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_FASTMEM_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_FASTMEM_FORCE_NOISO);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_FASTMEM_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_FASTMEM_FORCE_NOISO);
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}
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if (cfg.rtc_slowmem_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_SLOWMEM_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_SLOWMEM_FORCE_NOISO);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_SLOWMEM_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_SLOWMEM_FORCE_NOISO);
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}
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if (cfg.rtc_peri_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);
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}
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if (cfg.wifi_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
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}
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/*
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#ifdef CONFIG_CHIP_IS_ESP32
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if (cfg.rom_mem_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN);
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}
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#endif
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*/
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if (cfg.deep_slp) {
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/* redundant ? People may not want to touch such registers after init
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG,
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RTC_CNTL_DG_PAD_FORCE_ISO | RTC_CNTL_DG_PAD_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG,
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RTC_CNTL_DG_WRAP_FORCE_PU | RTC_CNTL_DG_WRAP_FORCE_PD);
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#ifdef CONFIG_CHIP_IS_ESP32
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
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#endif
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*/
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, RTC_CNTL_DBG_ATTEN_DEFAULT);
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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// Shut down parts of RTC which may have been left enabled by the wireless drivers
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
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RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
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RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 6);
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}
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/* enable VDDSDIO control by state machine */
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REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
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REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp);
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REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
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REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
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}
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void rtc_sleep_set_wakeup_time(uint64_t t)
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{
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
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}
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uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
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{
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REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
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REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
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if (reject_opt != 0) {
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REG_SET_BIT(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN);
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}
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/* Start entry into sleep mode */
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
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while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
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RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
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;
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}
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/* In deep sleep mode, we never get here */
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uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
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SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
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RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
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/* restore config if it is a light sleep */
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if (lslp_mem_inf_fpu)
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{
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rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
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rtc_sleep_pd(pd_cfg);
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}
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/* move setting from init to sleep, so we don't need to have this any more
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* restore DBG_ATTEN to the default value
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, RTC_CNTL_DBG_ATTEN_DEFAULT);
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*/
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return reject;
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}
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