Omar Chebib 752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' ... G0: RISC-V targets have now an independent G0 layer See merge request espressif/esp-idf!17926		2022-06-16 11:53:39 +08:00
..
include	esp_hw_support: Add esp_cpu.h abstraction and API	2022-06-14 14:30:58 +08:00
CMakeLists.txt	G0: RISC-V targets have now an independent G0 layer	2022-06-14 15:00:53 +08:00
instruction_decode.c	interrupt: filter out reserved int number by decoding risc-v JAL instruction	2021-01-05 15:39:46 +08:00
interrupt.c	esp_hw_support: Add esp_cpu.h abstraction and API	2022-06-14 14:30:58 +08:00
linker.lf	arch: move stdatomic	2021-02-26 18:40:00 +08:00
project_include.cmake	build system: removed target component	2022-05-24 09:12:59 +08:00
vectors.S	riscv: Adds support for returning from exception handler	2022-02-24 08:55:40 +00:00