mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
a9fda54d39
This commit updates the visibility of various header files and cleans up some unnecessary inclusions. Also, this commit removes certain header include paths which were maintained for backward compatibility.
253 lines
6.9 KiB
C
253 lines
6.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "soc/dport_access.h"
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#include "soc/system_reg.h"
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#include "esp_bit_defs.h"
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#include "soc/assist_debug_reg.h"
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#include "esp_attr.h"
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#include "riscv/csr.h"
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#include "riscv/semihosting.h"
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/*performance counter*/
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#define CSR_PCER_MACHINE 0x7e0
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#define CSR_PCMR_MACHINE 0x7e1
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#define CSR_PCCR_MACHINE 0x7e2
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/*fast gpio*/
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#define CSR_GPIO_OEN_USER 0x803
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#define CSR_GPIO_IN_USER 0x804
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#define CSR_GPIO_OUT_USER 0x805
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#ifdef __cplusplus
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extern "C" {
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#endif
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static inline int IRAM_ATTR cpu_ll_get_core_id(void)
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{
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#if SOC_CPU_CORES_NUM == 1
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return 0; // No need to check core ID on single core hardware
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#else
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int cpuid;
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cpuid = RV_READ_CSR(mhartid);
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return cpuid;
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#endif
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}
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static inline void cpu_ll_enable_cycle_count(void)
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{
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RV_WRITE_CSR(CSR_PCER_MACHINE,1);
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RV_WRITE_CSR(CSR_PCMR_MACHINE,1);
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return;
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}
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static inline uint32_t IRAM_ATTR cpu_ll_get_cycle_count(void)
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{
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uint32_t result;
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result = RV_READ_CSR(CSR_PCCR_MACHINE);
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return result;
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}
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static inline void IRAM_ATTR cpu_ll_set_cycle_count(uint32_t val)
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{
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RV_WRITE_CSR(CSR_PCCR_MACHINE, val);
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}
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static inline void* cpu_ll_get_sp(void)
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{
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void *sp;
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asm volatile ("mv %0, sp;" : "=r" (sp));
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return sp;
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}
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static inline void cpu_ll_init_hwloop(void)
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{
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// Nothing needed here for ESP32-C3
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}
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FORCE_INLINE_ATTR bool cpu_ll_is_debugger_attached(void)
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{
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return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
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}
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static inline void cpu_ll_set_breakpoint(int id, uint32_t pc)
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{
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if (cpu_ll_is_debugger_attached()) {
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/* If we want to set breakpoint which when hit transfers control to debugger
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* we need to set `action` in `mcontrol` to 1 (Enter Debug Mode).
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* That `action` value is supported only when `dmode` of `tdata1` is set.
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* But `dmode` can be modified by debugger only (from Debug Mode).
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*
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* So when debugger is connected we use special syscall to ask it to set breakpoint for us.
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*/
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long args[] = {true, id, (long)pc};
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int ret = semihosting_call_noerrno(ESP_SEMIHOSTING_SYS_BREAKPOINT_SET, args);
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if (ret == 0) {
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return;
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}
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}
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/* The code bellow sets breakpoint which will trigger `Breakpoint` exception
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* instead transfering control to debugger. */
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RV_WRITE_CSR(tselect,id);
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RV_SET_CSR(CSR_TCONTROL,TCONTROL_MTE);
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RV_SET_CSR(CSR_TDATA1, TDATA1_USER|TDATA1_MACHINE|TDATA1_EXECUTE);
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RV_WRITE_CSR(tdata2,pc);
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return;
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}
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static inline void cpu_ll_clear_breakpoint(int id)
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{
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if (cpu_ll_is_debugger_attached()) {
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/* see description in cpu_ll_set_breakpoint() */
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long args[] = {false, id};
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int ret = semihosting_call_noerrno(ESP_SEMIHOSTING_SYS_BREAKPOINT_SET, args);
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if (ret == 0){
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return;
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}
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}
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RV_WRITE_CSR(tselect,id);
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RV_CLEAR_CSR(CSR_TCONTROL,TCONTROL_MTE);
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RV_CLEAR_CSR(CSR_TDATA1, TDATA1_USER|TDATA1_MACHINE|TDATA1_EXECUTE);
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return;
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}
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static inline uint32_t cpu_ll_ptr_to_pc(const void* addr)
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{
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return ((uint32_t) addr);
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}
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static inline void* cpu_ll_pc_to_ptr(uint32_t pc)
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{
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return (void*) ((pc & 0x3fffffff) | 0x40000000);
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}
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static inline void cpu_ll_set_watchpoint(int id,
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const void* addr,
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size_t size,
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bool on_read,
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bool on_write)
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{
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uint32_t addr_napot;
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if (cpu_ll_is_debugger_attached()) {
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/* see description in cpu_ll_set_breakpoint() */
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long args[] = {true, id, (long)addr, (long)size,
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(long)((on_read ? ESP_SEMIHOSTING_WP_FLG_RD : 0) | (on_write ? ESP_SEMIHOSTING_WP_FLG_WR : 0))};
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int ret = semihosting_call_noerrno(ESP_SEMIHOSTING_SYS_WATCHPOINT_SET, args);
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if (ret == 0) {
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return;
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}
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}
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RV_WRITE_CSR(tselect,id);
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RV_SET_CSR(CSR_TCONTROL, TCONTROL_MPTE | TCONTROL_MTE);
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RV_SET_CSR(CSR_TDATA1, TDATA1_USER|TDATA1_MACHINE);
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RV_SET_CSR_FIELD(CSR_TDATA1, (long unsigned int) TDATA1_MATCH, 1);
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// add 0 in napot encoding
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addr_napot = ((uint32_t) addr) | ((size >> 1) - 1);
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if (on_read) {
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RV_SET_CSR(CSR_TDATA1, TDATA1_LOAD);
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}
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if (on_write) {
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RV_SET_CSR(CSR_TDATA1, TDATA1_STORE);
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}
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RV_WRITE_CSR(tdata2,addr_napot);
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return;
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}
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static inline void cpu_ll_clear_watchpoint(int id)
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{
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if (cpu_ll_is_debugger_attached()) {
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/* see description in cpu_ll_set_breakpoint() */
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long args[] = {false, id};
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int ret = semihosting_call_noerrno(ESP_SEMIHOSTING_SYS_WATCHPOINT_SET, args);
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if (ret == 0){
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return;
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}
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}
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RV_WRITE_CSR(tselect,id);
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RV_CLEAR_CSR(CSR_TCONTROL,TCONTROL_MTE);
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RV_CLEAR_CSR(CSR_TDATA1, TDATA1_USER|TDATA1_MACHINE);
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RV_CLEAR_CSR_FIELD(CSR_TDATA1, (long unsigned int) TDATA1_MATCH);
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RV_CLEAR_CSR(CSR_TDATA1, TDATA1_MACHINE);
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RV_CLEAR_CSR(CSR_TDATA1, TDATA1_LOAD|TDATA1_STORE|TDATA1_EXECUTE);
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return;
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}
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static inline void cpu_ll_break(void)
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{
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asm volatile("ebreak\n");
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return;
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}
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static inline void cpu_ll_set_vecbase(const void* vecbase)
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{
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uintptr_t vecbase_int = (uintptr_t)vecbase;
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vecbase_int |= 1; // Set MODE field to treat MTVEC as a vector base address
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RV_WRITE_CSR(mtvec, vecbase_int);
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}
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static inline void cpu_ll_waiti(void)
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{
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if (cpu_ll_is_debugger_attached() && DPORT_REG_GET_BIT(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON) == 0) {
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/* when SYSTEM_CPU_WAIT_MODE_FORCE_ON is disabled in WFI mode SBA access to memory does not work for debugger,
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so do not enter that mode when debugger is connected */
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return;
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}
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asm volatile ("wfi\n");
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}
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static inline void cpu_ll_enable_dedic_gpio_output(uint32_t mask)
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{
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RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask);
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}
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static inline void cpu_ll_write_dedic_gpio_all(uint32_t value)
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{
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RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
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}
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static inline uint32_t cpu_ll_read_dedic_gpio_in(void)
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{
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uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
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return value;
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}
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static inline uint32_t cpu_ll_read_dedic_gpio_out(void)
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{
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uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
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return value;
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}
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static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value)
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{
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RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
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RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value));
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}
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static inline void cpu_ll_compare_and_set_native(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
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{
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uint32_t old_value;
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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old_value = *addr;
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if (old_value == compare) {
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*addr = *set;
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}
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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*set = old_value;
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}
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#ifdef __cplusplus
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}
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#endif
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