mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
ce388a4111
Refactored internal EMAC DMA access. Added MPLL acquire to manage access to the MPLL by multiple periphs.
467 lines
17 KiB
C
467 lines
17 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_ldo_psram.h"
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#include "esp_private/mspi_timing_tuning.h"
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#include "../esp_psram_impl.h"
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#include "hal/psram_ctrlr_ll.h"
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#include "hal/mspi_timing_tuning_ll.h"
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#include "clk_ctrl_os.h"
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// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
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#define PSRAM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
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#define AP_HEX_PSRAM_SYNC_READ 0x0000
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#define AP_HEX_PSRAM_SYNC_WRITE 0x8080
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#define AP_HEX_PSRAM_BURST_READ 0x2020
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#define AP_HEX_PSRAM_BURST_WRITE 0xA0A0
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#define AP_HEX_PSRAM_REG_READ 0x4040
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#define AP_HEX_PSRAM_REG_WRITE 0xC0C0
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#define AP_HEX_PSRAM_RD_CMD_BITLEN 16
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#define AP_HEX_PSRAM_WR_CMD_BITLEN 16
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#define AP_HEX_PSRAM_ADDR_BITLEN 32
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#if CONFIG_SPIRAM_SPEED_250M
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#define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(18-1))
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#define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(9-1))
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#define AP_HEX_PSRAM_RD_LATENCY 6
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#define AP_HEX_PSRAM_WR_LATENCY 3
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#elif CONFIG_SPIRAM_SPEED_200M
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#define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(14-1))
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#define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(7-1))
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#define AP_HEX_PSRAM_RD_LATENCY 4
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#define AP_HEX_PSRAM_WR_LATENCY 1
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#else
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#define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
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#define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
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#define AP_HEX_PSRAM_RD_LATENCY 2
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#define AP_HEX_PSRAM_WR_LATENCY 2
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#endif
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#define AP_HEX_PSRAM_VENDOR_ID 0xD
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#define AP_HEX_PSRAM_CS_SETUP_TIME 4
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#define AP_HEX_PSRAM_CS_HOLD_TIME 4
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#define AP_HEX_PSRAM_CS_ECC_HOLD_TIME 4
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#define AP_HEX_PSRAM_CS_HOLD_DELAY 3
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#define AP_HEX_PSRAM_MPLL_DEFAULT_FREQ_MHZ 400
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typedef struct {
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union {
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struct {
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uint8_t drive_str: 2;
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uint8_t read_latency: 3;
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uint8_t lt: 1;
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uint8_t rsvd6: 1;
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uint8_t tso: 1;
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};
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uint8_t val;
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} mr0;
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union {
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struct {
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uint8_t vendor_id: 5;
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uint8_t rsvd0_2: 2;
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uint8_t ulp: 1;
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};
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uint8_t val;
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} mr1;
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union {
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struct {
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uint8_t density: 3;
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uint8_t dev_id: 2;
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uint8_t kgd: 3;
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};
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uint8_t val;
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} mr2;
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union {
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struct {
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uint8_t rsvd3_7: 4;
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uint8_t srf: 2;
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uint8_t rsvd0: 1;
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uint8_t rbx_en: 1;
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};
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uint8_t val;
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} mr3;
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union {
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struct {
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uint8_t pasr: 3;
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uint8_t rf: 2;
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uint8_t wr_latency: 3;
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};
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uint8_t val;
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} mr4;
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union {
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struct {
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uint8_t bl: 2;
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uint8_t bt: 1;
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uint8_t rbx: 1;
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uint8_t rsvd5: 2;
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uint8_t x16: 1;
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uint8_t rsvd7: 1;
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};
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uint8_t val;
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} mr8;
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} hex_psram_mode_reg_t;
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static const char* TAG = "hex_psram";
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static uint32_t s_psram_size; //this stands for physical psram size in bytes
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/**
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* Common psram transaction
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*/
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static void s_psram_common_transaction(uint32_t mspi_id,
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uint32_t cmd, uint32_t cmd_bitlen,
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uint32_t addr, uint32_t addr_bitlen,
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uint32_t dummy_bits,
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uint8_t* mosi_data, uint32_t mosi_bitlen,
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uint8_t* miso_data, uint32_t miso_bitlen,
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bool is_write_erase_operation)
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{
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psram_ctrlr_ll_common_transaction(mspi_id, cmd, cmd_bitlen, addr, addr_bitlen, dummy_bits,
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mosi_data, mosi_bitlen, miso_data, miso_bitlen,
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is_write_erase_operation);
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}
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/**
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* Initialise mode registers of the PSRAM
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*/
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static void s_init_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *mode_reg_config)
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{
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int cmd_len = 16;
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uint32_t addr = 0x0;
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int addr_bit_len = 32;
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int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN;
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hex_psram_mode_reg_t mode_reg = {0};
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int data_bit_len = 16;
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//read MR0 and MR1
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_READ, cmd_len,
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addr, addr_bit_len,
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dummy,
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NULL, 0,
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&mode_reg.mr0.val, data_bit_len,
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false);
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addr = 0x4;
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//read MR4 and MR8
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_READ, cmd_len,
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addr, addr_bit_len,
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dummy,
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NULL, 0,
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&mode_reg.mr4.val, data_bit_len,
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false);
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//modify
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mode_reg.mr0.lt = mode_reg_config->mr0.lt;
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mode_reg.mr0.read_latency = mode_reg_config->mr0.read_latency;
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mode_reg.mr0.drive_str = mode_reg_config->mr0.drive_str;
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mode_reg.mr4.wr_latency = mode_reg_config->mr4.wr_latency;
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//write
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addr = 0x0;
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_WRITE, cmd_len,
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addr, addr_bit_len,
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0,
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&mode_reg.mr0.val, 16,
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NULL, 0,
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false);
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addr = 0x4;
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_WRITE, cmd_len,
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addr, addr_bit_len,
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0,
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&mode_reg.mr4.val, 16,
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NULL, 0,
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false);
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//read
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addr = 0x8;
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data_bit_len = 8;
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_READ, cmd_len,
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addr, addr_bit_len,
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dummy,
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NULL, 0,
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&mode_reg.mr8.val, data_bit_len,
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false);
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//modify
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mode_reg.mr8.bt = mode_reg_config->mr8.bt;
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mode_reg.mr8.bl = mode_reg_config->mr8.bl;
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mode_reg.mr8.rbx = mode_reg_config->mr8.rbx;
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mode_reg.mr8.x16 = mode_reg_config->mr8.x16;
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//write
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_WRITE, cmd_len,
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addr, addr_bit_len,
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0,
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&mode_reg.mr8.val, 16,
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NULL, 0,
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false);
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}
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static void s_get_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *out_reg)
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{
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int cmd_len = 16;
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int addr_bit_len = 32;
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int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN;
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int data_bit_len = 16;
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//Read MR0~1 register
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_READ, cmd_len,
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0x0, addr_bit_len,
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dummy,
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NULL, 0,
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&out_reg->mr0.val, data_bit_len,
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false);
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//Read MR2~3 register
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_READ, cmd_len,
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0x2, addr_bit_len,
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dummy,
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NULL, 0,
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&out_reg->mr2.val, data_bit_len,
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false);
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data_bit_len = 8;
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//Read MR4 register
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_READ, cmd_len,
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0x4, addr_bit_len,
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dummy,
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NULL, 0,
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&out_reg->mr4.val, data_bit_len,
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false);
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//Read MR8 register
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s_psram_common_transaction(spi_num,
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AP_HEX_PSRAM_REG_READ, cmd_len,
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0x8, addr_bit_len,
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dummy,
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NULL, 0,
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&out_reg->mr8.val, data_bit_len,
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false);
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}
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static void s_print_psram_info(hex_psram_mode_reg_t *reg_val)
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{
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ESP_EARLY_LOGI(TAG, "vendor id : 0x%02x (%s)", reg_val->mr1.vendor_id, reg_val->mr1.vendor_id == 0x0d ? "AP" : "UNKNOWN");
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ESP_EARLY_LOGI(TAG, "Latency : 0x%02x (%s)", reg_val->mr0.lt, reg_val->mr0.lt == 1 ? "Fixed" : "Variable");
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ESP_EARLY_LOGI(TAG, "DriveStr. : 0x%02x (%d Ohm)", reg_val->mr0.drive_str, reg_val->mr0.drive_str < 2 ? 25 * (reg_val->mr0.drive_str + 1) : 100 * (reg_val->mr0.drive_str - 1));
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ESP_EARLY_LOGI(TAG, "dev id : 0x%02x (generation %d)", reg_val->mr2.dev_id, reg_val->mr2.dev_id + 1);
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ESP_EARLY_LOGI(TAG, "density : 0x%02x (%d Mbit)", reg_val->mr2.density, reg_val->mr2.density == 0x1 ? 32 :
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reg_val->mr2.density == 0X3 ? 64 :
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reg_val->mr2.density == 0x5 ? 128 :
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reg_val->mr2.density == 0x7 ? 256 : 0);
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ESP_EARLY_LOGI(TAG, "good-die : 0x%02x (%s)", reg_val->mr2.kgd, reg_val->mr2.kgd == 6 ? "Pass" : "Fail");
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ESP_EARLY_LOGI(TAG, "SRF : 0x%02x (%s Refresh)", reg_val->mr3.srf, reg_val->mr3.srf == 0x1 ? "Fast" : "Slow");
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ESP_EARLY_LOGI(TAG, "BurstType : 0x%02x (%s Wrap)", reg_val->mr8.bt, reg_val->mr8.bt == 1 && reg_val->mr8.bl != 3 ? "Hybrid" : "");
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ESP_EARLY_LOGI(TAG, "BurstLen : 0x%02x (%d Byte)", reg_val->mr8.bl, reg_val->mr8.bl == 0x00 ? 16 :
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reg_val->mr8.bl == 0x01 ? 32 :
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reg_val->mr8.bl == 0x10 ? 64 : 2048);
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ESP_EARLY_LOGI(TAG, "BitMode : 0x%02x (%s Mode)", reg_val->mr8.x16, reg_val->mr8.x16 == 1 ? "X16" : "X8");
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ESP_EARLY_LOGI(TAG, "Readlatency : 0x%02x (%d cycles@%s)", reg_val->mr0.read_latency, reg_val->mr0.read_latency * 2 + 6,
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reg_val->mr0.lt == 1 ? "Fixed" : "Variable");
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ESP_EARLY_LOGI(TAG, "DriveStrength: 0x%02x (1/%d)", reg_val->mr0.drive_str, reg_val->mr0.drive_str == 0x00 ? 1 :
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reg_val->mr0.drive_str == 0x01 ? 2 :
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reg_val->mr0.drive_str == 0x02 ? 4 : 8);
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}
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static void s_config_mspi_for_psram(void)
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{
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//Config Write CMD phase for SPI0 to access PSRAM
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psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_WR_CMD_BITLEN, AP_HEX_PSRAM_SYNC_WRITE);
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//Config Read CMD phase for SPI0 to access PSRAM
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psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_RD_CMD_BITLEN, AP_HEX_PSRAM_SYNC_READ);
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//Config ADDR phase
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psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_ADDR_BITLEN);
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psram_ctrlr_ll_enable_4byte_addr(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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//Config RD/WR Dummy phase
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psram_ctrlr_ll_set_wr_dummy(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_WR_DUMMY_BITLEN);
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psram_ctrlr_ll_set_rd_dummy(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_RD_DUMMY_BITLEN);
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psram_ctrlr_ll_enable_variable_dummy(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_enable_wr_dummy_level_control(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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//DDR
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psram_ctrlr_ll_enable_ddr_wr_data_swap(PSRAM_CTRLR_LL_MSPI_ID_2, false);
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psram_ctrlr_ll_enable_ddr_rd_data_swap(PSRAM_CTRLR_LL_MSPI_ID_2, false);
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psram_ctrlr_ll_enable_ddr_mode(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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//Line mode
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psram_ctrlr_ll_enable_oct_line_mode(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_enable_hex_data_line_mode(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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#if CONFIG_SPIRAM_USE_8LINE_MODE
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psram_ctrlr_ll_enable_hex_data_line_mode(PSRAM_CTRLR_LL_MSPI_ID_2, false);
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#endif
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//AXI
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psram_ctrlr_ll_enable_axi_access(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_enable_wr_splice(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_enable_rd_splice(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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}
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static void s_set_psram_cs_timing(void)
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{
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psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_CS_SETUP_TIME);
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psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_CS_HOLD_TIME);
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psram_ctrlr_ll_set_cs_hold_delay(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_CS_HOLD_DELAY);
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#if CONFIG_SPIRAM_ECC_ENABLE
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psram_ctrlr_ll_set_cs_hold_ecc(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_CS_ECC_HOLD_TIME);
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#endif
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}
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#if CONFIG_SPIRAM_ECC_ENABLE
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static void s_mspi_ecc_show_info(void)
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{
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for (int i = 0; i < PSRAM_CTRLR_LL_PMS_REGION_NUMS; i++) {
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ESP_EARLY_LOGV(TAG, "region[%d] addr: 0x%08x", i, psram_ctrlr_ll_get_pms_region_start_addr(PSRAM_CTRLR_LL_MSPI_ID_2, i));
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ESP_EARLY_LOGV(TAG, "region[%d] size: 0x%08x", i, psram_ctrlr_ll_get_pms_region_size(PSRAM_CTRLR_LL_MSPI_ID_2, i));
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}
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uint32_t page_size = psram_ctrlr_ll_get_page_size(PSRAM_CTRLR_LL_MSPI_ID_2);
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ESP_EARLY_LOGV(TAG, "ECC page size: %d", page_size);
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}
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/**
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* Enable error correcting code feature
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*
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* Can add an input parameter for selecting ECC mode if needed
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*/
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static void s_configure_psram_ecc(void)
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{
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psram_ctrlr_ll_enable_16to18_ecc(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_enable_skip_page_corner(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_2, 2048);
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psram_ctrlr_ll_enable_ecc_addr_conversion(PSRAM_CTRLR_LL_MSPI_ID_2, 2048);
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/**
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* Enable ECC region 0 (ACE0)
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* Default: ACE0 range: 0 ~ 256MB
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* Current Hex PSRAM is 8MB, ACE0 is enough
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*/
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psram_ctrlr_ll_enable_pms_region_ecc(PSRAM_CTRLR_LL_MSPI_ID_2, 0, true);
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ESP_EARLY_LOGI(TAG, "ECC is enabled");
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s_mspi_ecc_show_info();
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}
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#endif //#if CONFIG_SPIRAM_ECC_ENABLE
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esp_err_t esp_psram_impl_enable(void)
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{
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#if SOC_CLK_MPLL_SUPPORTED
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periph_rtc_mpll_early_acquire();
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periph_rtc_mpll_freq_set(AP_HEX_PSRAM_MPLL_DEFAULT_FREQ_MHZ * 1000000, NULL);
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#endif
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PSRAM_RCC_ATOMIC() {
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psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_reset_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2);
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psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_MPLL);
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psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_MPLL);
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}
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mspi_timing_ll_pin_drv_set(2);
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mspi_timing_ll_enable_dqs(true);
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s_set_psram_cs_timing();
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#if CONFIG_SPIRAM_ECC_ENABLE
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s_configure_psram_ecc();
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#endif
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//enter MSPI slow mode to init PSRAM device registers
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psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_2, 40);
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psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_3, 40);
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psram_ctrlr_ll_enable_dll(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_enable_dll(PSRAM_CTRLR_LL_MSPI_ID_3, true);
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static hex_psram_mode_reg_t mode_reg = {};
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mode_reg.mr0.lt = 1;
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mode_reg.mr0.read_latency = AP_HEX_PSRAM_RD_LATENCY;
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mode_reg.mr0.drive_str = 0;
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mode_reg.mr4.wr_latency = AP_HEX_PSRAM_WR_LATENCY;
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mode_reg.mr8.bl = 3;
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mode_reg.mr8.bt = 0;
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mode_reg.mr8.rbx = 1;
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mode_reg.mr8.x16 = 1;
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#if CONFIG_SPIRAM_USE_8LINE_MODE
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mode_reg.mr8.x16 = 0;
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#endif
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s_init_psram_mode_reg(PSRAM_CTRLR_LL_MSPI_ID_3, &mode_reg);
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//Print PSRAM info
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s_get_psram_mode_reg(PSRAM_CTRLR_LL_MSPI_ID_3, &mode_reg);
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if (mode_reg.mr1.vendor_id != AP_HEX_PSRAM_VENDOR_ID) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", mode_reg.mr1.vendor_id);
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return ESP_ERR_NOT_SUPPORTED;
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}
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s_print_psram_info(&mode_reg);
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s_psram_size = mode_reg.mr2.density == 0x1 ? PSRAM_SIZE_4MB :
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mode_reg.mr2.density == 0X3 ? PSRAM_SIZE_8MB :
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mode_reg.mr2.density == 0x5 ? PSRAM_SIZE_16MB :
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mode_reg.mr2.density == 0x7 ? PSRAM_SIZE_32MB :
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mode_reg.mr2.density == 0x6 ? PSRAM_SIZE_64MB : 0;
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|
|
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#if CONFIG_SPIRAM_SPEED_250M
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if (mode_reg.mr2.density == 0x7) {
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ESP_EARLY_LOGE(TAG, "PSRAM Not support 250MHz speed");
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return ESP_ERR_NOT_SUPPORTED;
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}
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#endif
|
|
|
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s_config_mspi_for_psram();
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mspi_timing_psram_tuning();
|
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psram_ctrlr_ll_enable_variable_dummy(PSRAM_CTRLR_LL_MSPI_ID_2, true);
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psram_ctrlr_ll_enable_variable_dummy(PSRAM_CTRLR_LL_MSPI_ID_3, true);
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|
|
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return ESP_OK;
|
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}
|
|
|
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uint8_t esp_psram_impl_get_cs_io(void)
|
|
{
|
|
ESP_EARLY_LOGI(TAG, "psram CS IO is dedicated");
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return -1;
|
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}
|
|
|
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esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
|
|
{
|
|
if (!out_size_bytes) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
|
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*out_size_bytes = s_psram_size;
|
|
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
|
}
|
|
|
|
/**
|
|
* This function is to get the available physical psram size in bytes.
|
|
* If ECC is enabled, available PSRAM size will be 7/8 times its physical size.
|
|
*/
|
|
esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
|
|
{
|
|
if (!out_size_bytes) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
|
|
#if CONFIG_SPIRAM_ECC_ENABLE
|
|
*out_size_bytes = s_psram_size * 7 / 8;
|
|
#else
|
|
*out_size_bytes = s_psram_size;
|
|
#endif
|
|
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
|
}
|