mirror of
https://github.com/espressif/esp-idf.git
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150 lines
4.0 KiB
C
150 lines
4.0 KiB
C
/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** DS_Y_MEM register
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* memory that stores Y
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*/
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#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
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#define DS_Y_MEM_SIZE_BYTES 512
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/** DS_M_MEM register
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* memory that stores M
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*/
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#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
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#define DS_M_MEM_SIZE_BYTES 512
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/** DS_RB_MEM register
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* memory that stores Rb
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*/
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#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
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#define DS_RB_MEM_SIZE_BYTES 512
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/** DS_BOX_MEM register
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* memory that stores BOX
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*/
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#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
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#define DS_BOX_MEM_SIZE_BYTES 48
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/** DS_IV_MEM register
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* memory that stores IV
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*/
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#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
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#define DS_IV_MEM_SIZE_BYTES 16
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/** DS_X_MEM register
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* memory that stores X
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*/
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#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
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#define DS_X_MEM_SIZE_BYTES 512
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/** DS_Z_MEM register
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* memory that stores Z
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*/
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#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
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#define DS_Z_MEM_SIZE_BYTES 512
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/** DS_SET_START_REG register
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* DS start control register
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*/
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#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
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/** DS_SET_START : WT; bitpos: [0]; default: 0;
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* set this bit to start DS operation.
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*/
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#define DS_SET_START (BIT(0))
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#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S)
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#define DS_SET_START_V 0x00000001U
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#define DS_SET_START_S 0
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/** DS_SET_CONTINUE_REG register
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* DS continue control register
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*/
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#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
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/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
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* set this bit to continue DS operation.
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*/
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#define DS_SET_CONTINUE (BIT(0))
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#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
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#define DS_SET_CONTINUE_V 0x00000001U
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#define DS_SET_CONTINUE_S 0
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/** DS_SET_FINISH_REG register
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* DS finish control register
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*/
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#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
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/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
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* Set this bit to finish DS process.
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*/
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#define DS_SET_FINISH (BIT(0))
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#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S)
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#define DS_SET_FINISH_V 0x00000001U
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#define DS_SET_FINISH_S 0
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/** DS_QUERY_BUSY_REG register
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* DS query busy register
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*/
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#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
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/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
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* digital signature state. 1'b0: idle, 1'b1: busy
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*/
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#define DS_QUERY_BUSY (BIT(0))
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#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
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#define DS_QUERY_BUSY_V 0x00000001U
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#define DS_QUERY_BUSY_S 0
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/** DS_QUERY_KEY_WRONG_REG register
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* DS query key-wrong counter register
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*/
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#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
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/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
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* digital signature key wrong counter
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*/
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#define DS_QUERY_KEY_WRONG 0x0000000FU
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#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
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#define DS_QUERY_KEY_WRONG_V 0x0000000FU
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#define DS_QUERY_KEY_WRONG_S 0
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/** DS_QUERY_CHECK_REG register
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* DS query check result register
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*/
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#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
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/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
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* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
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*/
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#define DS_MD_ERROR (BIT(0))
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#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S)
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#define DS_MD_ERROR_V 0x00000001U
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#define DS_MD_ERROR_S 0
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/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
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* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
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*/
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#define DS_PADDING_BAD (BIT(1))
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#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
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#define DS_PADDING_BAD_V 0x00000001U
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#define DS_PADDING_BAD_S 1
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/** DS_DATE_REG register
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* DS version control register
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*/
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#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
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/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624;
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* ds version information
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*/
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#define DS_DATE 0x3FFFFFFFU
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#define DS_DATE_M (DS_DATE_V << DS_DATE_S)
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#define DS_DATE_V 0x3FFFFFFFU
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#define DS_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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