mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
366 lines
9.3 KiB
C
366 lines
9.3 KiB
C
/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: configure_register */
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/** Type of lp_clk_conf register
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* need_des
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*/
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typedef union {
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struct {
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/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
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* need_des
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*/
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uint32_t slow_clk_sel:2;
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/** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
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* need_des
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*/
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uint32_t fast_clk_sel:2;
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/** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0;
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* need_des
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*/
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uint32_t lp_peri_div_num:8;
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uint32_t reserved_12:20;
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};
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uint32_t val;
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} lp_clkrst_lp_clk_conf_reg_t;
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/** Type of lp_clk_po_en register
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* need_des
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*/
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typedef union {
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struct {
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/** aon_slow_oen : R/W; bitpos: [0]; default: 1;
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* need_des
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*/
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uint32_t aon_slow_oen:1;
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/** aon_fast_oen : R/W; bitpos: [1]; default: 1;
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* need_des
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*/
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uint32_t aon_fast_oen:1;
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/** sosc_oen : R/W; bitpos: [2]; default: 1;
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* need_des
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*/
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uint32_t sosc_oen:1;
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/** fosc_oen : R/W; bitpos: [3]; default: 1;
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* need_des
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*/
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uint32_t fosc_oen:1;
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/** osc32k_oen : R/W; bitpos: [4]; default: 1;
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* need_des
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*/
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uint32_t osc32k_oen:1;
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/** xtal32k_oen : R/W; bitpos: [5]; default: 1;
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* need_des
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*/
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uint32_t xtal32k_oen:1;
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/** core_efuse_oen : R/W; bitpos: [6]; default: 1;
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* need_des
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*/
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uint32_t core_efuse_oen:1;
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/** slow_oen : R/W; bitpos: [7]; default: 1;
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* need_des
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*/
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uint32_t slow_oen:1;
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/** fast_oen : R/W; bitpos: [8]; default: 1;
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* need_des
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*/
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uint32_t fast_oen:1;
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/** rng_oen : R/W; bitpos: [9]; default: 1;
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* need_des
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*/
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uint32_t rng_oen:1;
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/** lpbus_oen : R/W; bitpos: [10]; default: 1;
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* need_des
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*/
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uint32_t lpbus_oen:1;
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uint32_t reserved_11:21;
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};
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uint32_t val;
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} lp_clkrst_lp_clk_po_en_reg_t;
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/** Type of lp_clk_en register
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* need_des
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** fast_ori_gate : R/W; bitpos: [31]; default: 0;
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* need_des
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*/
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uint32_t fast_ori_gate:1;
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};
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uint32_t val;
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} lp_clkrst_lp_clk_en_reg_t;
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/** Type of lp_rst_en register
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* need_des
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*/
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typedef union {
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struct {
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uint32_t reserved_0:28;
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/** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
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* need_des
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*/
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uint32_t aon_efuse_core_reset_en:1;
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/** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
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* need_des
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*/
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uint32_t lp_timer_reset_en:1;
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/** wdt_reset_en : R/W; bitpos: [30]; default: 0;
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* need_des
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*/
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uint32_t wdt_reset_en:1;
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/** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
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* need_des
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*/
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uint32_t ana_peri_reset_en:1;
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};
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uint32_t val;
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} lp_clkrst_lp_rst_en_reg_t;
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/** Type of reset_cause register
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* need_des
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*/
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typedef union {
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struct {
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/** reset_cause : RO; bitpos: [4:0]; default: 0;
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* need_des
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*/
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uint32_t reset_cause:5;
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/** core0_reset_flag : RO; bitpos: [5]; default: 1;
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* need_des
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*/
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uint32_t core0_reset_flag:1;
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uint32_t reserved_6:23;
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/** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
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* need_des
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*/
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uint32_t core0_reset_cause_clr:1;
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/** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
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* need_des
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*/
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uint32_t core0_reset_flag_set:1;
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/** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
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* need_des
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*/
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uint32_t core0_reset_flag_clr:1;
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};
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uint32_t val;
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} lp_clkrst_reset_cause_reg_t;
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/** Type of cpu_reset register
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* need_des
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*/
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typedef union {
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struct {
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uint32_t reserved_0:22;
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/** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
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* need_des
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*/
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uint32_t rtc_wdt_cpu_reset_length:3;
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/** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
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* need_des
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*/
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uint32_t rtc_wdt_cpu_reset_en:1;
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/** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
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* need_des
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*/
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uint32_t cpu_stall_wait:5;
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/** cpu_stall_en : R/W; bitpos: [31]; default: 0;
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* need_des
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*/
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uint32_t cpu_stall_en:1;
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};
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uint32_t val;
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} lp_clkrst_cpu_reset_reg_t;
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/** Type of fosc_cntl register
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* need_des
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*/
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typedef union {
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struct {
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uint32_t reserved_0:22;
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/** fosc_dfreq : R/W; bitpos: [31:22]; default: 600;
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* need_des
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*/
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uint32_t fosc_dfreq:10;
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};
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uint32_t val;
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} lp_clkrst_fosc_cntl_reg_t;
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/** Type of rc32k_cntl register
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* need_des
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*/
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typedef union {
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struct {
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uint32_t reserved_0:22;
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/** rc32k_dfreq : R/W; bitpos: [31:22]; default: 650;
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* need_des
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*/
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uint32_t rc32k_dfreq:10;
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};
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uint32_t val;
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} lp_clkrst_rc32k_cntl_reg_t;
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/** Type of clk_to_hp register
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* need_des
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*/
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typedef union {
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struct {
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uint32_t reserved_0:28;
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/** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
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* need_des
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*/
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uint32_t icg_hp_xtal32k:1;
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/** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
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* need_des
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*/
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uint32_t icg_hp_sosc:1;
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/** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
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* need_des
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*/
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uint32_t icg_hp_osc32k:1;
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/** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
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* need_des
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*/
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uint32_t icg_hp_fosc:1;
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};
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uint32_t val;
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} lp_clkrst_clk_to_hp_reg_t;
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/** Type of lpmem_force register
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* need_des
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
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* need_des
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*/
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uint32_t lpmem_clk_force_on:1;
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};
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uint32_t val;
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} lp_clkrst_lpmem_force_reg_t;
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/** Type of lpperi register
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* need_des
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*/
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typedef union {
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struct {
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uint32_t reserved_0:12;
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/** lp_bletimer_div_num : R/W; bitpos: [23:12]; default: 0;
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* need_des
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*/
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uint32_t lp_bletimer_div_num:12;
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/** lp_bletimer_32k_sel : R/W; bitpos: [25:24]; default: 0;
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* need_des
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*/
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uint32_t lp_bletimer_32k_sel:2;
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/** lp_sel_osc_slow : R/W; bitpos: [26]; default: 0;
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* need_des
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*/
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uint32_t lp_sel_osc_slow:1;
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/** lp_sel_osc_fast : R/W; bitpos: [27]; default: 0;
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* need_des
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*/
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uint32_t lp_sel_osc_fast:1;
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/** lp_sel_xtal : R/W; bitpos: [28]; default: 0;
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* need_des
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*/
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uint32_t lp_sel_xtal:1;
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/** lp_sel_xtal32k : R/W; bitpos: [29]; default: 1;
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* need_des
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*/
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uint32_t lp_sel_xtal32k:1;
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/** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0;
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* need_des
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*/
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uint32_t lp_i2c_clk_sel:1;
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/** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0;
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* need_des
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*/
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uint32_t lp_uart_clk_sel:1;
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};
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uint32_t val;
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} lp_clkrst_lpperi_reg_t;
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/** Type of xtal32k register
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* need_des
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*/
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typedef union {
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struct {
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uint32_t reserved_0:22;
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/** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
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* need_des
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*/
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uint32_t dres_xtal32k:3;
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/** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
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* need_des
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*/
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uint32_t dgm_xtal32k:3;
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/** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
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* need_des
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*/
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uint32_t dbuf_xtal32k:1;
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/** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
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* need_des
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*/
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uint32_t dac_xtal32k:3;
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};
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uint32_t val;
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} lp_clkrst_xtal32k_reg_t;
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/** Type of date register
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* need_des
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*/
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typedef union {
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struct {
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/** clkrst_date : R/W; bitpos: [30:0]; default: 35680896;
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* need_des
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*/
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uint32_t clkrst_date:31;
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/** clk_en : R/W; bitpos: [31]; default: 0;
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* need_des
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*/
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uint32_t clk_en:1;
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};
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uint32_t val;
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} lp_clkrst_date_reg_t;
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typedef struct {
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volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
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volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
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volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
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volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
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volatile lp_clkrst_reset_cause_reg_t reset_cause;
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volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
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volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
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volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
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volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
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volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
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volatile lp_clkrst_lpperi_reg_t lpperi;
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volatile lp_clkrst_xtal32k_reg_t xtal32k;
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uint32_t reserved_030[243];
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volatile lp_clkrst_date_reg_t date;
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} lp_clkrst_dev_t;
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extern lp_clkrst_dev_t LP_CLKRST;
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#ifndef __cplusplus
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_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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