mirror of
https://github.com/espressif/esp-idf.git
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147 lines
5.4 KiB
C
147 lines
5.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* This file will be redesigned into MMU driver, to maintain all the external
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* memory contexts including:
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* - Flash
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* - PSRAM
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* - DDR
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*
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* Now only MMU-PSRAM related private APIs
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*/
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "soc/ext_mem_defs.h"
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#include "hal/cache_types.h"
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#include "hal/cache_ll.h"
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#include "esp_private/mmu.h"
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/cache.h"
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#endif
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
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//page_size - 1, where page_size on s2 and s3 is always 0x10000. To be refactored by MMU driver
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#define INVALID_PHY_PAGE 0xffff
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const static char *TAG = "mmu_psram";
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//TODO IDF-4387
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static uint32_t page0_mapped = 0;
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static uint32_t page0_page = INVALID_PHY_PAGE;
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#endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page)
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{
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uint32_t page_id = start_page;
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/**
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* TODO IDF-4387
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* `Cache_Count_Flash_Pages` seems give wrong results. Need to confirm this.
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* FOR NOW, leave these logics just as it used to be.
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*
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* The rom API will be redesigned into a MMU driver layer function
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*/
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uint32_t flash_pages = 0;
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#if CONFIG_IDF_TARGET_ESP32S2
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flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_IBUS0, &page0_mapped);
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flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_IBUS1, &page0_mapped);
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#elif CONFIG_IDF_TARGET_ESP32S3
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flash_pages += Cache_Count_Flash_Pages(CACHE_IBUS, &page0_mapped);
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#endif
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if ((flash_pages + page_id) > BYTES_TO_MMU_PAGE(psram_size)) {
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ESP_EARLY_LOGE(TAG, "PSRAM space not enough for the Flash instructions, need %d B, from %d B to %d B",
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MMU_PAGE_TO_BYTES(flash_pages), MMU_PAGE_TO_BYTES(start_page), MMU_PAGE_TO_BYTES(flash_pages + page_id));
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return ESP_FAIL;
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}
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//Enable the most high bus, which is used for copying FLASH .text to PSRAM
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cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, SOC_EXTRAM_DATA_HIGH, 0);
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cache_ll_l1_enable_bus(0, bus_mask);
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#if !CONFIG_FREERTOS_UNICORE
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bus_mask = cache_ll_l1_get_bus(1, SOC_EXTRAM_DATA_HIGH, 0);
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cache_ll_l1_enable_bus(1, bus_mask);
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#endif
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instruction_flash_page_info_init(page_id);
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#if CONFIG_IDF_TARGET_ESP32S2
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page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS0, IRAM0_ADDRESS_LOW, page_id, &page0_page);
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page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS1, IRAM1_ADDRESS_LOW, page_id, &page0_page);
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#elif CONFIG_IDF_TARGET_ESP32S3
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page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_IBUS, IRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
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#endif
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ESP_EARLY_LOGV(TAG, "after copy instruction, page_id is %d", page_id);
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ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM");
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*out_page = page_id - start_page;
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return ESP_OK;
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}
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#endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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#if CONFIG_SPIRAM_RODATA
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esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page)
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{
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uint32_t page_id = start_page;
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/**
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* TODO IDF-4387
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* `Cache_Count_Flash_Pages` seems give wrong results. Need to confirm this.
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* FOR NOW, leave these logics just as it used to be.
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*
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* The rom API will be redesigned into a MMU driver layer function
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*/
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uint32_t flash_pages = 0;
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#if CONFIG_IDF_TARGET_ESP32S2
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flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_IBUS2, &page0_mapped);
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flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_DBUS0, &page0_mapped);
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flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_DBUS1, &page0_mapped);
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flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_DBUS2, &page0_mapped);
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#elif CONFIG_IDF_TARGET_ESP32S3
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flash_pages += Cache_Count_Flash_Pages(CACHE_DBUS, &page0_mapped);
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#endif
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if ((flash_pages + page_id) > BYTES_TO_MMU_PAGE(psram_size)) {
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ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, need to copy to %d B.", MMU_PAGE_TO_BYTES(flash_pages + page_id));
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return ESP_FAIL;
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}
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//Enable the most high bus, which is used for copying FLASH .text to PSRAM
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cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, SOC_EXTRAM_DATA_HIGH, 0);
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cache_ll_l1_enable_bus(0, bus_mask);
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#if !CONFIG_FREERTOS_UNICORE
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bus_mask = cache_ll_l1_get_bus(1, SOC_EXTRAM_DATA_HIGH, 0);
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cache_ll_l1_enable_bus(1, bus_mask);
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#endif
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rodata_flash_page_info_init(page_id);
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#if CONFIG_IDF_TARGET_ESP32S2
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page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, DROM0_ADDRESS_LOW, page_id, &page0_page);
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page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS0, DRAM0_ADDRESS_LOW, page_id, &page0_page);
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page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS1, DRAM1_ADDRESS_LOW, page_id, &page0_page);
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page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS2, DPORT_ADDRESS_LOW, page_id, &page0_page);
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#elif CONFIG_IDF_TARGET_ESP32S3
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page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_DBUS, DRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
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#endif
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ESP_EARLY_LOGV(TAG, "after copy rodata, page_id is %d", page_id);
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ESP_EARLY_LOGI(TAG, "Read only data copied and mapped to SPIRAM");
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*out_page = page_id - start_page;
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return ESP_OK;
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}
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#endif //#if CONFIG_SPIRAM_RODATA
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