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138 lines
6.8 KiB
C
138 lines
6.8 KiB
C
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef BOOTLOADER_BUILD
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#include <stdlib.h>
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/soc_memory_layout.h"
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#include "esp_heap_caps.h"
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#include "sdkconfig.h"
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/* Memory layout for ESP32 SoC */
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/*
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Memory type descriptors. These describe the capabilities of a type of memory in the SoC. Each type of memory
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map consist of one or more regions in the address space.
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Each type contains an array of prioritised capabilities; types with later entries are only taken if earlier
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ones can't fulfill the memory request.
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The prioritised capabilities work roughly like this:
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- For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions,
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finally eat into the application memory.
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- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
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- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
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- Most other malloc caps only fit in one region anyway.
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*/
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const soc_memory_type_desc_t soc_memory_types[] = {
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//Type 0: DRAM
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{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false},
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// Type 1: DRAM used for startup stacks
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{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, true},
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//Type 2: DRAM which has an alias on the I-port
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{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, false},
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//Type 3: IRAM
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//In ESP32S2beta, All IRAM region are available by D-port (D/IRAM).
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{ "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
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//Type 4: SPI SRAM data
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//TODO, in fact, part of them support EDMA, to be supported.
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{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
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//Type 5: SPI SRAM data from AHB DBUS3, slower than normal
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//TODO, add a bit to control the access of it
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#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
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{ "SPIRAM(Slow)", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
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#endif
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};
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const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
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/*
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Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
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Because of requirements in the coalescing code which merges adjacent regions, this list should always be sorted
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from low to high start address.
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*/
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const soc_memory_region_t soc_memory_regions[] = {
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#ifdef CONFIG_SPIRAM
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{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available
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#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
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{ SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH - SOC_SLOW_EXTRAM_DATA_LOW, 5, 0}, //SPI SRAM, if available
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#endif
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#endif
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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#if CONFIG_ESP32S2_DATA_CACHE_0KB
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{ 0x3FFB2000, 0x2000, 2, 0x40022000}, //Block 1, can be use as I/D cache memory
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{ 0x3FFB4000, 0x2000, 2, 0x40024000}, //Block 2, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#elif CONFIG_ESP32S2_DATA_CACHE_8KB
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{ 0x3FFB4000, 0x2000, 2, 0x40024000}, //Block 2, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#else
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#endif
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#else
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#if CONFIG_ESP32S2_DATA_CACHE_0KB
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{ 0x3FFB4000, 0x2000, 2, 0x40024000}, //Block 2, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#elif CONFIG_ESP32S2_DATA_CACHE_8KB
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#endif
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#endif
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{ 0x3FFB8000, 0x4000, 2, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory
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{ 0x3FFBC000, 0x4000, 2, 0x4002C000}, //Block 5, can be remapped to ROM, can be used as trace memory
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{ 0x3FFC0000, 0x4000, 2, 0x40030000}, //Block 6, can be used as trace memory
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{ 0x3FFC4000, 0x4000, 2, 0x40034000}, //Block 7, can be used as trace memory
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{ 0x3FFC8000, 0x4000, 2, 0x40038000}, //Block 8, can be used as trace memory
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{ 0x3FFCC000, 0x4000, 2, 0x4003C000}, //Block 9, can be used as trace memory
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{ 0x3FFD0000, 0x4000, 2, 0x40040000}, //Block 10, can be used as trace memory
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{ 0x3FFD4000, 0x4000, 2, 0x40044000}, //Block 11, can be used as trace memory
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{ 0x3FFD8000, 0x4000, 2, 0x40048000}, //Block 12, can be used as trace memory
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{ 0x3FFDC000, 0x4000, 2, 0x4004C000}, //Block 13, can be used as trace memory
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{ 0x3FFE0000, 0x4000, 2, 0x40050000}, //Block 14, can be used as trace memory
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{ 0x3FFE4000, 0x4000, 2, 0x40054000}, //Block 15, can be used as trace memory
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{ 0x3FFE8000, 0x4000, 2, 0x40058000}, //Block 16, can be used as trace memory
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{ 0x3FFEC000, 0x4000, 2, 0x4005C000}, //Block 17, can be used as trace memory
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{ 0x3FFF0000, 0x4000, 2, 0x40060000}, //Block 18, can be used for MAC dump, can be used as trace memory
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{ 0x3FFF4000, 0x4000, 2, 0x40064000}, //Block 19, can be used for MAC dump, can be used as trace memory
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{ 0x3FFF8000, 0x4000, 2, 0x40068000}, //Block 20, can be used for MAC dump, can be used as trace memory
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{ 0x3FFFC000, 0x4000, 1, 0x4006C000}, //Block 21, can be used for MAC dump, can be used as trace memory, used for startup stack
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};
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const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_memory_region_t);
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extern int _data_start_xtos;
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/* Reserved memory regions
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These are removed from the soc_memory_regions array when heaps are created.
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*/
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//ROM data region
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SOC_RESERVE_MEMORY_REGION(0x3fffc000, (intptr_t)&_data_start_xtos, rom_data_region);
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// TODO: soc_memory_layout: handle trace memory regions - IDF-750
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#ifdef CONFIG_SPIRAM
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SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
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#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
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SOC_RESERVE_MEMORY_REGION( SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH, extram_slow_data_region); //SPI RAM(Slow) gets added later if needed, in spiram.c; reserve it for now
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#endif
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#endif
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#endif
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