mirror of
https://github.com/espressif/esp-idf.git
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04b95f3567
Commit 891eb3b0 was fixing an issue with PS and EPC1 not being
preserved after the window spill procedure. It did so by saving PS in
a2 and EPC1 in a4. However the a4 register may be a live register of
another window in the call stack, and if it is overwritten and then
spilled to the stack, then the corresponding register value will end
up being corrupted. In practice the problem would show up as an
IllegalInstruction exception, when trying to return from a function
when a0 value was 0x40020.
Fix by using a0 register instead of a4 as scratch. Also fix a comment
about xthal_save_extra_nw, as this function in fact doesn't clobber
a4 or a5 because XCHAL_NCP_NUM_ATMPS is defined as 1.
Closes https://github.com/espressif/esp-idf/issues/5758
660 lines
24 KiB
ArmAsm
660 lines
24 KiB
ArmAsm
/*******************************************************************************
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Copyright (c) 2006-2015 Cadence Design Systems Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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--------------------------------------------------------------------------------
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XTENSA CONTEXT SAVE AND RESTORE ROUTINES
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Low-level Call0 functions for handling generic context save and restore of
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registers not specifically addressed by the interrupt vectors and handlers.
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Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
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Except for the calls to RTOS functions, this code is generic to Xtensa.
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Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
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save regs (A12-A15), which is always the case if the handlers are coded in C.
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However A12, A13 are made available as scratch registers for interrupt dispatch
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code, so are presumed saved anyway, and are always restored even in Call0 ABI.
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Only A14, A15 are truly handled as callee-save regs.
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Because Xtensa is a configurable architecture, this port supports all user
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generated configurations (except restrictions stated in the release notes).
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This is accomplished by conditional compilation using macros and functions
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defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
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Only the processor state included in your configuration is saved and restored,
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including any processor state added by user configuration options or TIE.
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*******************************************************************************/
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/* Warn nicely if this file gets named with a lowercase .s instead of .S: */
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#define NOERROR #
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NOERROR: .error "C preprocessor needed for this file: make sure its filename\
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ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
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#include "xtensa_rtos.h"
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#include "xtensa_context.h"
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#include "xt_asm_utils.h"
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#ifdef XT_USE_OVLY
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#include <xtensa/overlay_os_asm.h>
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#endif
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.text
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/*******************************************************************************
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_xt_context_save
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!! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
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Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
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interrupt stack frame defined in xtensa_rtos.h.
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Its counterpart is _xt_context_restore (which also restores A12, A13).
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Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
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This function preserves A12 & A13 in order to provide the caller with 2 scratch
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regs that need not be saved over the call to this function. The choice of which
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2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
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to avoid moving data more than necessary. Caller can assign regs accordingly.
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Entry Conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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Original A12, A13 have already been saved in the interrupt stack frame.
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Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
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point of interruption.
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If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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Exit conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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A12, A13 as at entry (preserved).
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If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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*******************************************************************************/
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.global _xt_context_save
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.type _xt_context_save,@function
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.align 4
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.literal_position
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.align 4
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_xt_context_save:
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s32i a2, sp, XT_STK_A2
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s32i a3, sp, XT_STK_A3
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s32i a4, sp, XT_STK_A4
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s32i a5, sp, XT_STK_A5
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s32i a6, sp, XT_STK_A6
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s32i a7, sp, XT_STK_A7
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s32i a8, sp, XT_STK_A8
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s32i a9, sp, XT_STK_A9
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s32i a10, sp, XT_STK_A10
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s32i a11, sp, XT_STK_A11
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/*
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Call0 ABI callee-saved regs a12-15 do not need to be saved here.
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a12-13 are the caller's responsibility so it can use them as scratch.
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So only need to save a14-a15 here for Windowed ABI (not Call0).
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*/
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#ifndef __XTENSA_CALL0_ABI__
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s32i a14, sp, XT_STK_A14
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s32i a15, sp, XT_STK_A15
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#endif
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rsr a3, SAR
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s32i a3, sp, XT_STK_SAR
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#if XCHAL_HAVE_LOOPS
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rsr a3, LBEG
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s32i a3, sp, XT_STK_LBEG
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rsr a3, LEND
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s32i a3, sp, XT_STK_LEND
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rsr a3, LCOUNT
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s32i a3, sp, XT_STK_LCOUNT
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#endif
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#ifdef XT_USE_SWPRI
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/* Save virtual priority mask */
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movi a3, _xt_vpri_mask
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l32i a3, a3, 0
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s32i a3, sp, XT_STK_VPRI
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#endif
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#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
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mov a9, a0 /* preserve ret addr */
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#endif
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s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
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s32i a13, sp, XT_STK_TMP1
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s32i a9, sp, XT_STK_TMP2
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l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */
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l32i a13, sp, XT_STK_A13
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l32i a9, sp, XT_STK_A9
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#if XCHAL_EXTRA_SA_SIZE > 0
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addi a2, sp, XT_STK_EXTRA /* where to save it */
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# if XCHAL_EXTRA_SA_ALIGN > 16
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movi a3, -XCHAL_EXTRA_SA_ALIGN
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and a2, a2, a3 /* align dynamically >16 bytes */
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# endif
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call0 xthal_save_extra_nw /* destroys a0,2,3 */
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#endif
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#ifndef __XTENSA_CALL0_ABI__
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#ifdef XT_USE_OVLY
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l32i a9, sp, XT_STK_PC /* recover saved PC */
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_xt_overlay_get_state a9, a12, a13
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s32i a9, sp, XT_STK_OVLY /* save overlay state */
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#endif
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/* SPILL_ALL_WINDOWS macro requires window overflow exceptions to be enabled,
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* i.e. PS.EXCM cleared and PS.WOE set.
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* Since we are going to clear PS.EXCM, we also need to increase INTLEVEL
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* at least to XCHAL_EXCM_LEVEL. This matches that value of effective INTLEVEL
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* at entry (CINTLEVEL=max(PS.INTLEVEL, XCHAL_EXCM_LEVEL) when PS.EXCM is set.
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* Since WindowOverflow exceptions will trigger inside SPILL_ALL_WINDOWS,
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* need to save/restore EPC1 as well.
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* Note: even though a4-a15 are saved into the exception frame, we should not
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* clobber them until after SPILL_ALL_WINDOWS. This is because these registers
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* may contain live windows belonging to previous frames in the call stack.
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* These frames will be spilled by SPILL_ALL_WINDOWS, and if the register was
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* used as a temporary by this code, the temporary value would get stored
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* onto the stack, instead of the real value.
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*/
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rsr a2, PS /* to be restored after SPILL_ALL_WINDOWS */
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movi a0, PS_INTLEVEL_MASK
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and a3, a2, a0 /* get the current INTLEVEL */
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bgeui a3, XCHAL_EXCM_LEVEL, 1f /* calculate max(INTLEVEL, XCHAL_EXCM_LEVEL) */
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movi a3, XCHAL_EXCM_LEVEL
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1:
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movi a0, PS_UM | PS_WOE /* clear EXCM, enable window overflow, set new INTLEVEL */
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or a3, a3, a0
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wsr a3, ps
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rsr a0, EPC1 /* to be restored after SPILL_ALL_WINDOWS */
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addi sp, sp, XT_STK_FRMSZ /* go back to spill register region */
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SPILL_ALL_WINDOWS /* place the live register windows there */
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addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with context save*/
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wsr a2, PS /* restore to the value at entry */
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rsync
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wsr a0, EPC1 /* likewise */
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#endif /* __XTENSA_CALL0_ABI__ */
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l32i a12, sp, XT_STK_TMP0 /* restore the temp saved registers */
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l32i a13, sp, XT_STK_TMP1 /* our return address is there */
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l32i a9, sp, XT_STK_TMP2
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#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
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mov a0, a9 /* retrieve ret addr */
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#endif
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ret
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/*******************************************************************************
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_xt_context_restore
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!! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
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Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
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ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
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stack frame defined in xtensa_rtos.h .
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Its counterpart is _xt_context_save (whose caller saved A12, A13).
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Caller is responsible to restore PC, PS, A0, A1 (SP).
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Entry Conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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Exit conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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Other processor state except PC, PS, A0, A1 (SP), is as at the point
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of interruption.
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*******************************************************************************/
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.global _xt_context_restore
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.type _xt_context_restore,@function
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.align 4
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.literal_position
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.align 4
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_xt_context_restore:
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#if XCHAL_EXTRA_SA_SIZE > 0
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/*
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NOTE: Normally the xthal_restore_extra_nw macro only affects address
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registers a2-a5. It is theoretically possible for Xtensa processor
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designers to write TIE that causes more address registers to be
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affected, but it is generally unlikely. If that ever happens,
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more registers need to be saved/restored around this macro invocation.
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Here we only assume a13 is preserved.
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Future Xtensa tools releases might limit the regs that can be affected.
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*/
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mov a13, a0 /* preserve ret addr */
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addi a2, sp, XT_STK_EXTRA /* where to find it */
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# if XCHAL_EXTRA_SA_ALIGN > 16
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movi a3, -XCHAL_EXTRA_SA_ALIGN
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and a2, a2, a3 /* align dynamically >16 bytes */
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# endif
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call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */
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mov a0, a13 /* retrieve ret addr */
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#endif
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#if XCHAL_HAVE_LOOPS
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l32i a2, sp, XT_STK_LBEG
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l32i a3, sp, XT_STK_LEND
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wsr a2, LBEG
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l32i a2, sp, XT_STK_LCOUNT
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wsr a3, LEND
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wsr a2, LCOUNT
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#endif
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#ifdef XT_USE_OVLY
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/*
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If we are using overlays, this is a good spot to check if we need
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to restore an overlay for the incoming task. Here we have a bunch
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of registers to spare. Note that this step is going to use a few
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bytes of storage below SP (SP-20 to SP-32) if an overlay is going
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to be restored.
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*/
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l32i a2, sp, XT_STK_PC /* retrieve PC */
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l32i a3, sp, XT_STK_PS /* retrieve PS */
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l32i a4, sp, XT_STK_OVLY /* retrieve overlay state */
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l32i a5, sp, XT_STK_A1 /* retrieve stack ptr */
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_xt_overlay_check_map a2, a3, a4, a5, a6
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s32i a2, sp, XT_STK_PC /* save updated PC */
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s32i a3, sp, XT_STK_PS /* save updated PS */
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#endif
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#ifdef XT_USE_SWPRI
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/* Restore virtual interrupt priority and interrupt enable */
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movi a3, _xt_intdata
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l32i a4, a3, 0 /* a4 = _xt_intenable */
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l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */
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and a4, a4, a5
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wsr a4, INTENABLE /* update INTENABLE */
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s32i a5, a3, 4 /* restore _xt_vpri_mask */
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#endif
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l32i a3, sp, XT_STK_SAR
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l32i a2, sp, XT_STK_A2
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wsr a3, SAR
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l32i a3, sp, XT_STK_A3
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l32i a4, sp, XT_STK_A4
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l32i a5, sp, XT_STK_A5
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l32i a6, sp, XT_STK_A6
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l32i a7, sp, XT_STK_A7
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l32i a8, sp, XT_STK_A8
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l32i a9, sp, XT_STK_A9
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l32i a10, sp, XT_STK_A10
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l32i a11, sp, XT_STK_A11
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/*
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Call0 ABI callee-saved regs a12-15 do not need to be restored here.
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However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
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so need to be restored anyway, despite being callee-saved in Call0.
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*/
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l32i a12, sp, XT_STK_A12
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l32i a13, sp, XT_STK_A13
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#ifndef __XTENSA_CALL0_ABI__
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l32i a14, sp, XT_STK_A14
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l32i a15, sp, XT_STK_A15
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#endif
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ret
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/*******************************************************************************
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_xt_coproc_init
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Initializes global co-processor management data, setting all co-processors
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to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
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Called during initialization of the RTOS, before any threads run.
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This may be called from normal Xtensa single-threaded application code which
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might use co-processors. The Xtensa run-time initialization enables all
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co-processors. They must remain enabled here, else a co-processor exception
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might occur outside of a thread, which the exception handler doesn't expect.
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Entry Conditions:
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Xtensa single-threaded run-time environment is in effect.
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No thread is yet running.
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Exit conditions:
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None.
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Obeys ABI conventions per prototype:
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void _xt_coproc_init(void)
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*******************************************************************************/
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#if XCHAL_CP_NUM > 0
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.global _xt_coproc_init
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.type _xt_coproc_init,@function
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.align 4
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.literal_position
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.align 4
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_xt_coproc_init:
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ENTRY0
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/* Initialize thread co-processor ownerships to 0 (unowned). */
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movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */
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addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */
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movi a4, 0 /* a4 = 0 (unowned) */
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1: s32i a4, a2, 0
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addi a2, a2, 4
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bltu a2, a3, 1b
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RET0
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#endif
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/*******************************************************************************
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_xt_coproc_release
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Releases any and all co-processors owned by a given thread. The thread is
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identified by it's co-processor state save area defined in xtensa_context.h .
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Must be called before a thread's co-proc save area is deleted to avoid
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memory corruption when the exception handler tries to save the state.
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May be called when a thread terminates or completes but does not delete
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the co-proc save area, to avoid the exception handler having to save the
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thread's co-proc state before another thread can use it (optimization).
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Needs to be called on the processor the thread was running on. Unpinned threads
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won't have an entry here because they get pinned as soon they use a coprocessor.
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Entry Conditions:
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A2 = Pointer to base of co-processor state save area.
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Exit conditions:
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None.
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Obeys ABI conventions per prototype:
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void _xt_coproc_release(void * coproc_sa_base)
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*******************************************************************************/
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#if XCHAL_CP_NUM > 0
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.global _xt_coproc_release
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.type _xt_coproc_release,@function
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.align 4
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.literal_position
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.align 4
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_xt_coproc_release:
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ENTRY0 /* a2 = base of save area */
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getcoreid a5
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movi a3, XCHAL_CP_MAX << 2
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mull a5, a5, a3
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movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
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add a3, a3, a5
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addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */
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movi a5, 0 /* a5 = 0 (unowned) */
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rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */
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1: l32i a7, a3, 0 /* a7 = owner at a3 */
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bne a2, a7, 2f /* if (coproc_sa_base == owner) */
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s32i a5, a3, 0 /* owner = unowned */
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2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */
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bltu a3, a4, 1b /* repeat until end of array */
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3: wsr a6, PS /* restore interrupts */
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RET0
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#endif
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/*******************************************************************************
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_xt_coproc_savecs
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If there is a current thread and it has a coprocessor state save area, then
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save all callee-saved state into this area. This function is called from the
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solicited context switch handler. It calls a system-specific function to get
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the coprocessor save area base address.
|
|
|
|
Entry conditions:
|
|
- The thread being switched out is still the current thread.
|
|
- CPENABLE state reflects which coprocessors are active.
|
|
- Registers have been saved/spilled already.
|
|
|
|
Exit conditions:
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|
- All necessary CP callee-saved state has been saved.
|
|
- Registers a2-a7, a13-a15 have been trashed.
|
|
|
|
Must be called from assembly code only, using CALL0.
|
|
*******************************************************************************/
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|
#if XCHAL_CP_NUM > 0
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|
|
|
.extern _xt_coproc_sa_offset /* external reference */
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|
|
.global _xt_coproc_savecs
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|
.type _xt_coproc_savecs,@function
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|
.align 4
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|
.literal_position
|
|
.align 4
|
|
_xt_coproc_savecs:
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|
|
|
/* At entry, CPENABLE should be showing which CPs are enabled. */
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|
|
|
rsr a2, CPENABLE /* a2 = which CPs are enabled */
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|
beqz a2, .Ldone /* quick exit if none */
|
|
mov a14, a0 /* save return address */
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|
call0 XT_RTOS_CP_STATE /* get address of CP save area */
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|
mov a0, a14 /* restore return address */
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|
beqz a15, .Ldone /* if none then nothing to do */
|
|
s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */
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|
movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
|
|
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
|
|
|
|
#if XCHAL_CP0_SA_SIZE
|
|
bbci.l a2, 0, 2f /* CP 0 not enabled */
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|
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
|
|
add a3, a14, a15 /* a3 = save area for CP 0 */
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|
xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP1_SA_SIZE
|
|
bbci.l a2, 1, 2f /* CP 1 not enabled */
|
|
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
|
|
add a3, a14, a15 /* a3 = save area for CP 1 */
|
|
xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP2_SA_SIZE
|
|
bbci.l a2, 2, 2f
|
|
l32i a14, a13, 8
|
|
add a3, a14, a15
|
|
xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP3_SA_SIZE
|
|
bbci.l a2, 3, 2f
|
|
l32i a14, a13, 12
|
|
add a3, a14, a15
|
|
xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP4_SA_SIZE
|
|
bbci.l a2, 4, 2f
|
|
l32i a14, a13, 16
|
|
add a3, a14, a15
|
|
xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP5_SA_SIZE
|
|
bbci.l a2, 5, 2f
|
|
l32i a14, a13, 20
|
|
add a3, a14, a15
|
|
xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP6_SA_SIZE
|
|
bbci.l a2, 6, 2f
|
|
l32i a14, a13, 24
|
|
add a3, a14, a15
|
|
xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP7_SA_SIZE
|
|
bbci.l a2, 7, 2f
|
|
l32i a14, a13, 28
|
|
add a3, a14, a15
|
|
xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
.Ldone:
|
|
ret
|
|
#endif
|
|
|
|
|
|
/*******************************************************************************
|
|
_xt_coproc_restorecs
|
|
|
|
Restore any callee-saved coprocessor state for the incoming thread.
|
|
This function is called from coprocessor exception handling, when giving
|
|
ownership to a thread that solicited a context switch earlier. It calls a
|
|
system-specific function to get the coprocessor save area base address.
|
|
|
|
Entry conditions:
|
|
- The incoming thread is set as the current thread.
|
|
- CPENABLE is set up correctly for all required coprocessors.
|
|
- a2 = mask of coprocessors to be restored.
|
|
|
|
Exit conditions:
|
|
- All necessary CP callee-saved state has been restored.
|
|
- CPENABLE - unchanged.
|
|
- Registers a2-a7, a13-a15 have been trashed.
|
|
|
|
Must be called from assembly code only, using CALL0.
|
|
*******************************************************************************/
|
|
#if XCHAL_CP_NUM > 0
|
|
|
|
.global _xt_coproc_restorecs
|
|
.type _xt_coproc_restorecs,@function
|
|
.align 4
|
|
.literal_position
|
|
.align 4
|
|
_xt_coproc_restorecs:
|
|
|
|
mov a14, a0 /* save return address */
|
|
call0 XT_RTOS_CP_STATE /* get address of CP save area */
|
|
mov a0, a14 /* restore return address */
|
|
beqz a15, .Ldone2 /* if none then nothing to do */
|
|
l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */
|
|
xor a3, a3, a2 /* clear the ones being restored */
|
|
s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */
|
|
movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
|
|
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
|
|
|
|
#if XCHAL_CP0_SA_SIZE
|
|
bbci.l a2, 0, 2f /* CP 0 not enabled */
|
|
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
|
|
add a3, a14, a15 /* a3 = save area for CP 0 */
|
|
xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP1_SA_SIZE
|
|
bbci.l a2, 1, 2f /* CP 1 not enabled */
|
|
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
|
|
add a3, a14, a15 /* a3 = save area for CP 1 */
|
|
xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP2_SA_SIZE
|
|
bbci.l a2, 2, 2f
|
|
l32i a14, a13, 8
|
|
add a3, a14, a15
|
|
xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP3_SA_SIZE
|
|
bbci.l a2, 3, 2f
|
|
l32i a14, a13, 12
|
|
add a3, a14, a15
|
|
xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP4_SA_SIZE
|
|
bbci.l a2, 4, 2f
|
|
l32i a14, a13, 16
|
|
add a3, a14, a15
|
|
xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP5_SA_SIZE
|
|
bbci.l a2, 5, 2f
|
|
l32i a14, a13, 20
|
|
add a3, a14, a15
|
|
xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP6_SA_SIZE
|
|
bbci.l a2, 6, 2f
|
|
l32i a14, a13, 24
|
|
add a3, a14, a15
|
|
xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
#if XCHAL_CP7_SA_SIZE
|
|
bbci.l a2, 7, 2f
|
|
l32i a14, a13, 28
|
|
add a3, a14, a15
|
|
xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
2:
|
|
#endif
|
|
|
|
.Ldone2:
|
|
ret
|
|
|
|
#endif
|
|
|
|
|