mirror of
https://github.com/espressif/esp-idf.git
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222 lines
9.3 KiB
C
222 lines
9.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct uhci_dev_s {
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union {
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struct {
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uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/
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uint32_t rx_rst: 1; /*Write 1 then write 0 to this bit to reset encode state machine.*/
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uint32_t uart0_ce: 1; /*Set this bit to link up HCI and UART0.*/
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uint32_t uart1_ce: 1; /*Set this bit to link up HCI and UART1.*/
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uint32_t reserved4: 1;
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uint32_t seper_en: 1; /*Set this bit to separate the data frame using a special char.*/
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uint32_t head_en: 1; /*Set this bit to encode the data packet with a formatting header.*/
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uint32_t crc_rec_en: 1; /*Set this bit to enable UHCI to receive the 16 bit CRC.*/
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uint32_t uart_idle_eof_en: 1; /*If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state.*/
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uint32_t len_eof_en: 1; /*If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.*/
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uint32_t encode_crc_en: 1; /*Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.*/
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uint32_t clk_en: 1; /*1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.*/
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uint32_t uart_rx_brk_eof_en: 1; /*If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART.*/
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uint32_t reserved13: 19;
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};
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uint32_t val;
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} conf0;
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union {
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struct {
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uint32_t rx_start: 1; /*a*/
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uint32_t tx_start: 1; /*a*/
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uint32_t rx_hung: 1; /*a*/
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uint32_t tx_hung: 1; /*a*/
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uint32_t send_s_q: 1; /*a*/
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uint32_t send_a_q: 1; /*a*/
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uint32_t outlink_eof_err: 1; /*This is the interrupt raw bit. Triggered when there are some errors in EOF in the*/
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uint32_t app_ctrl0: 1; /*Soft control int raw bit.*/
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uint32_t app_ctrl1: 1; /*Soft control int raw bit.*/
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uint32_t reserved9: 23;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t rx_start: 1; /*a*/
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uint32_t tx_start: 1; /*a*/
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uint32_t rx_hung: 1; /*a*/
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uint32_t tx_hung: 1; /*a*/
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uint32_t send_s_q: 1; /*a*/
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uint32_t send_a_q: 1; /*a*/
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uint32_t outlink_eof_err: 1; /*a*/
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uint32_t app_ctrl0: 1; /*a*/
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uint32_t app_ctrl1: 1; /*a*/
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uint32_t reserved9: 23;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t rx_start: 1; /*a*/
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uint32_t tx_start: 1; /*a*/
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uint32_t rx_hung: 1; /*a*/
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uint32_t tx_hung: 1; /*a*/
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uint32_t send_s_q: 1; /*a*/
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uint32_t send_a_q: 1; /*a*/
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uint32_t outlink_eof_err: 1; /*a*/
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uint32_t app_ctrl0: 1; /*a*/
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uint32_t app_ctrl1: 1; /*a*/
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uint32_t reserved9: 23;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t rx_start: 1; /*a*/
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uint32_t tx_start: 1; /*a*/
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uint32_t rx_hung: 1; /*a*/
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uint32_t tx_hung: 1; /*a*/
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uint32_t send_s_q: 1; /*a*/
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uint32_t send_a_q: 1; /*a*/
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uint32_t outlink_eof_err: 1; /*a*/
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uint32_t app_ctrl0: 1; /*a*/
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uint32_t app_ctrl1: 1; /*a*/
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uint32_t reserved9: 23;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t check_sum_en: 1; /*a*/
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uint32_t check_seq_en: 1; /*a*/
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uint32_t crc_disable: 1; /*a*/
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uint32_t save_head: 1; /*a*/
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uint32_t tx_check_sum_re: 1; /*a*/
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uint32_t tx_ack_num_re: 1; /*a*/
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uint32_t reserved6: 1;
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uint32_t wait_sw_start: 1; /*a*/
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uint32_t sw_start: 1; /*a*/
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uint32_t reserved9: 12;
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uint32_t reserved21: 11;
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};
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uint32_t val;
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} conf1;
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union {
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struct {
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uint32_t rx_err_cause: 3; /*a*/
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uint32_t decode_state: 3; /*a*/
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} state0;
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union {
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struct {
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uint32_t encode_state: 3; /*a*/
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} state1;
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union {
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struct {
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uint32_t tx_c0_esc_en: 1; /*a*/
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uint32_t tx_db_esc_en: 1; /*a*/
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uint32_t tx_11_esc_en: 1; /*a*/
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uint32_t tx_13_esc_en: 1; /*a*/
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uint32_t rx_c0_esc_en: 1; /*a*/
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uint32_t rx_db_esc_en: 1; /*a*/
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uint32_t rx_11_esc_en: 1; /*a*/
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uint32_t rx_13_esc_en: 1; /*a*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} escape_conf;
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union {
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struct {
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uint32_t txfifo_timeout: 8; /*a*/
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uint32_t txfifo_timeout_shift: 3; /*a*/
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uint32_t txfifo_timeout_ena: 1; /*a*/
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uint32_t rxfifo_timeout: 8; /*a*/
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uint32_t rxfifo_timeout_shift: 3; /*a*/
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uint32_t rxfifo_timeout_ena: 1; /*a*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} hung_conf;
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union {
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struct {
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uint32_t ack_num: 3;
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uint32_t ack_num_load: 1; /*a*/
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} ack_num;
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uint32_t rx_head; /*a*/
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union {
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struct {
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uint32_t single_send_num: 3; /*a*/
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uint32_t single_send_en: 1; /*a*/
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uint32_t always_send_num: 3; /*a*/
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uint32_t always_send_en: 1; /*a*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} quick_sent;
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struct {
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uint32_t w_data[2]; /*a*/
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} q_data[7];
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union {
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struct {
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uint32_t seper_char: 8; /*a*/
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uint32_t seper_esc_char0: 8; /*a*/
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uint32_t seper_esc_char1: 8; /*a*/
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uint32_t reserved24: 8; /*a*/
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};
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uint32_t val;
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} esc_conf0;
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union {
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struct {
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uint32_t seq0: 8; /*a*/
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uint32_t seq0_char0: 8; /*a*/
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uint32_t seq0_char1: 8; /*a*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf1;
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union {
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struct {
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uint32_t seq1: 8; /*a*/
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uint32_t seq1_char0: 8; /*a*/
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uint32_t seq1_char1: 8; /*a*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf2;
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union {
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struct {
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uint32_t seq2: 8; /*a*/
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uint32_t seq2_char0: 8; /*a*/
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uint32_t seq2_char1: 8; /*a*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf3;
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union {
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struct {
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uint32_t thrs: 13; /*a*/
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uint32_t reserved13:19;
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};
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uint32_t val;
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} pkt_thres;
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uint32_t date; /*a*/
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} uhci_dev_t;
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extern uhci_dev_t UHCI0;
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extern uhci_dev_t UHCI1;
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#ifdef __cplusplus
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}
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#endif
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