mirror of
https://github.com/espressif/esp-idf.git
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16677b0d3c
peripheral enable/disable usually should be managed by driver itself, so make it as espressif private APIs, not recommended for user to use it in application code. However, if user want to re-write the driver or ports to other platform, this is still possible by including the header in this way: "esp_private/peripheral_ctrl.h"
482 lines
18 KiB
C
482 lines
18 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <sys/param.h>
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#include "esp_log.h"
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#include "esp_check.h"
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#include "driver/spi_master.h"
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#include "esp_private/periph_ctrl.h"
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#include "essl_internal.h"
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#include "essl_spi.h"
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#include "essl_spi/esp32s2_defs.h"
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/**
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* Initialise device function list of SPI by this macro.
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*/
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#define ESSL_SPI_DEFAULT_DEV_FUNC() (essl_dev_t) {\
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.get_tx_buffer_num = essl_spi_get_tx_buffer_num,\
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.update_tx_buffer_num = essl_spi_update_tx_buffer_num,\
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.get_rx_data_size = essl_spi_get_rx_data_size,\
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.update_rx_data_size = essl_spi_update_rx_data_size,\
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.send_packet = essl_spi_send_packet,\
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.get_packet = essl_spi_get_packet,\
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.write_reg = essl_spi_write_reg,\
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.read_reg = essl_spi_read_reg,\
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}
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static const char TAG[] = "essl_spi";
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typedef struct {
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spi_device_handle_t spi; // Pointer to SPI device handle.
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/* Master TX, Slave RX */
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struct {
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size_t sent_buf_num; // Number of TX buffers that has been sent out by the master.
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size_t slave_rx_buf_num; // Number of RX buffers laoded by the slave.
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uint16_t tx_buffer_size; /* Buffer size for Master TX / Slave RX direction.
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* Data with length within this size will still be regarded as one buffer.
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* E.g. 10 bytes data costs 2 buffers if the size is 8 bytes per buffer. */
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uint8_t tx_sync_reg; // The pre-negotiated register ID for Master-TX-SLAVE-RX synchronization. 1 word (4 Bytes) will be reserved for the synchronization.
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} master_out;
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/* Master RX, Slave TX */
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struct {
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size_t received_bytes; // Number of the RX bytes that has been received by the Master.
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size_t slave_tx_bytes; // Number of the TX bytes that has been loaded by the Slave
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uint8_t rx_sync_reg; // The pre-negotiated register ID for Master-RX-SLAVE-TX synchronization. 1 word (4 Bytes) will be reserved for the synchronization.
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} master_in;
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} essl_spi_context_t;
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static uint16_t get_hd_command(uint16_t cmd_i, uint32_t flags)
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{
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//have no prefixes
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if (cmd_i == CMD_HD_EN_QPI_REG) return cmd_i;
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//doesn't support 4-line commands
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if(flags & SPI_TRANS_MODE_QIO && flags & SPI_TRANS_MODE_DIOQIO_ADDR &&
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(cmd_i == CMD_HD_WR_END_REG || cmd_i == CMD_HD_INT0_REG ||
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cmd_i == CMD_HD_INT1_REG || cmd_i == CMD_HD_INT2_REG)) {
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//the transaction will be sent in corresponding 1/2/4 bit mode, without address and data.
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//the CMD will have no 0xA- prefix
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return cmd_i;
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}
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if (flags & SPI_TRANS_MODE_DIO) {
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if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
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return cmd_i | CMD_HD_DIO_MODE;
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} else {
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return cmd_i | CMD_HD_DOUT_MODE;
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}
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} else if (flags & SPI_TRANS_MODE_QIO) {
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if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
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return cmd_i | CMD_HD_QIO_MODE;
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} else {
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return cmd_i | CMD_HD_QOUT_MODE;
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}
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}
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return cmd_i | CMD_HD_ONEBIT_MODE;
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}
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static int get_hd_dummy_bits(uint32_t flags)
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{
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//dummy is always 4 cycles when dual or quad mode is enabled. Otherwise 8 cycles in normal mode.
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if (flags & (SPI_TRANS_MODE_DIO | SPI_TRANS_MODE_QIO)) {
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return 4;
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} else {
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return 8;
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}
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}
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esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags)
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{
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spi_transaction_ext_t t = {
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.base = {
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.cmd = get_hd_command(CMD_HD_RDBUF_REG, flags),
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.addr = addr % 72,
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.rxlength = len * 8,
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.rx_buffer = out_data,
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.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
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},
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.dummy_bits = get_hd_dummy_bits(flags),
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};
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return spi_device_transmit(spi, (spi_transaction_t*)&t);
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}
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esp_err_t essl_spi_rdbuf_polling(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags)
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{
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spi_transaction_ext_t t = {
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.base = {
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.cmd = get_hd_command(CMD_HD_RDBUF_REG, flags),
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.addr = addr % 72,
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.rxlength = len * 8,
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.rx_buffer = out_data,
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.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
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},
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.dummy_bits = get_hd_dummy_bits(flags),
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};
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return spi_device_polling_transmit(spi, (spi_transaction_t*)&t);
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}
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esp_err_t essl_spi_wrbuf(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags)
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{
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spi_transaction_ext_t t = {
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.base = {
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.cmd = get_hd_command(CMD_HD_WRBUF_REG, flags),
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.addr = addr % 72,
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.length = len * 8,
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.tx_buffer = data,
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.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
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},
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.dummy_bits = get_hd_dummy_bits(flags),
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};
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return spi_device_transmit(spi, (spi_transaction_t*)&t);
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}
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esp_err_t essl_spi_wrbuf_polling(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags)
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{
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spi_transaction_ext_t t = {
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.base = {
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.cmd = get_hd_command(CMD_HD_WRBUF_REG, flags),
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.addr = addr % 72,
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.length = len * 8,
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.tx_buffer = data,
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.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
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},
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.dummy_bits = get_hd_dummy_bits(flags),
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};
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return spi_device_polling_transmit(spi, (spi_transaction_t*)&t);
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}
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esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg_len, uint32_t flags)
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{
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spi_transaction_ext_t t = {
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.base = {
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.cmd = get_hd_command(CMD_HD_RDDMA_REG, flags),
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.rxlength = seg_len * 8,
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.rx_buffer = out_data,
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.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
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},
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.dummy_bits = get_hd_dummy_bits(flags),
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};
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return spi_device_transmit(spi, (spi_transaction_t*)&t);
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}
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esp_err_t essl_spi_rddma_done(spi_device_handle_t spi, uint32_t flags)
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{
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spi_transaction_t end_t = {
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.cmd = get_hd_command(CMD_HD_INT0_REG, flags),
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.flags = flags,
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};
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return spi_device_transmit(spi, &end_t);
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}
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esp_err_t essl_spi_rddma(spi_device_handle_t spi, uint8_t *out_data, int len, int seg_len, uint32_t flags)
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{
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if (!esp_ptr_dma_capable(out_data) || ((intptr_t)out_data % 4) != 0) {
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return ESP_ERR_INVALID_ARG;
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}
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seg_len = (seg_len > 0)? seg_len : len;
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uint8_t* read_ptr = out_data;
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esp_err_t ret = ESP_OK;
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while (len > 0) {
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int send_len = MIN(seg_len, len);
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ret = essl_spi_rddma_seg(spi, read_ptr, send_len, flags);
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if (ret != ESP_OK) return ret;
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len -= send_len;
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read_ptr += send_len;
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}
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return essl_spi_rddma_done(spi, flags);
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}
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esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int seg_len, uint32_t flags)
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{
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spi_transaction_ext_t t = {
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.base = {
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.cmd = get_hd_command(CMD_HD_WRDMA_REG, flags),
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.length = seg_len * 8,
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.tx_buffer = data,
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.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
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},
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.dummy_bits = get_hd_dummy_bits(flags),
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};
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return spi_device_transmit(spi, (spi_transaction_t*)&t);
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}
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esp_err_t essl_spi_wrdma_done(spi_device_handle_t spi, uint32_t flags)
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{
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spi_transaction_t end_t = {
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.cmd = get_hd_command(CMD_HD_WR_END_REG, flags),
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.flags = flags,
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};
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return spi_device_transmit(spi, &end_t);
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}
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esp_err_t essl_spi_wrdma(spi_device_handle_t spi, const uint8_t *data, int len, int seg_len, uint32_t flags)
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{
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if (!esp_ptr_dma_capable(data)) {
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return ESP_ERR_INVALID_ARG;
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}
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seg_len = (seg_len > 0)? seg_len : len;
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while (len > 0) {
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int send_len = MIN(seg_len, len);
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esp_err_t ret = essl_spi_wrdma_seg(spi, data, send_len, flags);
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if (ret != ESP_OK) return ret;
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len -= send_len;
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data += send_len;
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}
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return essl_spi_wrdma_done(spi, flags);
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}
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esp_err_t essl_spi_int(spi_device_handle_t spi, int int_n, uint32_t flags)
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{
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spi_transaction_t end_t = {
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.cmd = get_hd_command(CMD_HD_INT0_REG + int_n, flags),
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.flags = flags,
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};
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return spi_device_transmit(spi, &end_t);
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}
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//------------------------------------ APPEND MODE ----------------------------------//
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static uint32_t essl_spi_get_rx_data_size(void *arg);
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static esp_err_t essl_spi_update_rx_data_size(void *arg, uint32_t wait_ms);
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static uint32_t essl_spi_get_tx_buffer_num(void *arg);
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static esp_err_t essl_spi_update_tx_buffer_num(void *arg, uint32_t wait_ms);
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esp_err_t essl_spi_init_dev(essl_handle_t *out_handle, const essl_spi_config_t *init_config)
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{
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ESP_RETURN_ON_FALSE(init_config->spi, ESP_ERR_INVALID_STATE, TAG, "Check SPI initialization first");
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ESP_RETURN_ON_FALSE(init_config->tx_sync_reg <= (SOC_SPI_MAXIMUM_BUFFER_SIZE - 1) * 4, ESP_ERR_INVALID_ARG, TAG, "GPSPI supports %d-byte-width internal registers", SOC_SPI_MAXIMUM_BUFFER_SIZE);
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ESP_RETURN_ON_FALSE(init_config->rx_sync_reg <= (SOC_SPI_MAXIMUM_BUFFER_SIZE - 1) * 4, ESP_ERR_INVALID_ARG, TAG, "GPSPI supports %d-byte-width internal registers", SOC_SPI_MAXIMUM_BUFFER_SIZE);
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ESP_RETURN_ON_FALSE(init_config->tx_sync_reg != init_config->rx_sync_reg, ESP_ERR_INVALID_ARG, TAG, "Should use different word of registers for synchronization");
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essl_spi_context_t *context = calloc(1, sizeof(essl_spi_context_t));
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essl_dev_t *dev = calloc(1, sizeof(essl_dev_t));
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if (!context || !dev) {
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free(context);
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free(dev);
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return ESP_ERR_NO_MEM;
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}
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*context = (essl_spi_context_t) {
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.spi = *init_config->spi,
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.master_out.tx_buffer_size = init_config->tx_buf_size,
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.master_out.tx_sync_reg = init_config->tx_sync_reg,
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.master_in.rx_sync_reg = init_config->rx_sync_reg
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};
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*dev = ESSL_SPI_DEFAULT_DEV_FUNC();
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dev->args = context;
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*out_handle = dev;
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return ESP_OK;
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}
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esp_err_t essl_spi_deinit_dev(essl_handle_t handle)
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{
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ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, TAG, "ESSL SPI is not in use");
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free(handle->args);
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free(handle);
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return ESP_OK;
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}
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void essl_spi_reset_cnt(void *arg)
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{
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essl_spi_context_t *ctx = arg;
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if (ctx) {
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ctx->master_out.sent_buf_num = 0;
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ctx->master_in.received_bytes = 0;
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}
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}
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//------------------------------------ RX ----------------------------------//
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esp_err_t essl_spi_read_reg(void *arg, uint8_t addr, uint8_t *out_value, uint32_t wait_ms)
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{
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essl_spi_context_t *ctx = arg;
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ESP_RETURN_ON_FALSE(arg, ESP_ERR_INVALID_STATE, TAG, "Check ESSL SPI initialization first");
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uint8_t reserved_1_head = ctx->master_out.tx_sync_reg < ctx->master_in.rx_sync_reg ? ctx->master_out.tx_sync_reg : ctx->master_in.rx_sync_reg;
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uint8_t reserved_1_tail = reserved_1_head + 3;
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uint8_t reserved_2_head = ctx->master_out.tx_sync_reg < ctx->master_in.rx_sync_reg ? ctx->master_in.rx_sync_reg : ctx->master_out.tx_sync_reg;
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uint8_t reserved_2_tail = reserved_2_head + 3;
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ESP_RETURN_ON_FALSE(addr < reserved_1_head || (addr > reserved_1_tail && addr < reserved_2_head) || addr > reserved_2_tail, ESP_ERR_INVALID_ARG, TAG, "Invalid address");
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return essl_spi_rdbuf(ctx->spi, out_value, addr, sizeof(uint8_t), 0);
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}
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static uint32_t essl_spi_get_rx_data_size(void *arg)
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{
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essl_spi_context_t *ctx = arg;
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ESP_LOGV(TAG, "slave tx buffer: %d bytes, master has read: %d bytes", ctx->master_in.slave_tx_bytes, ctx->master_in.received_bytes);
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return ctx->master_in.slave_tx_bytes - ctx->master_in.received_bytes;
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}
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static esp_err_t essl_spi_update_rx_data_size(void *arg, uint32_t wait_ms)
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{
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essl_spi_context_t *ctx = arg;
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uint32_t updated_size;
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uint32_t previous_size;
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esp_err_t ret;
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ret = essl_spi_rdbuf_polling(ctx->spi, (uint8_t *)&previous_size, ctx->master_in.rx_sync_reg, sizeof(uint32_t), 0);
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if (ret != ESP_OK) {
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return ret;
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}
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/**
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* Read until the last 2 reading result are same. Reason:
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* SPI transaction is carried on per 1 Byte. So when Master is reading the shared register, if the
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* register value is changed by Slave at this time, Master may get wrong data.
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*/
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while (1) {
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ret = essl_spi_rdbuf_polling(ctx->spi, (uint8_t *)&updated_size, ctx->master_in.rx_sync_reg, sizeof(uint32_t), 0);
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if (ret != ESP_OK) {
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return ret;
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}
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if (updated_size == previous_size) {
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ctx->master_in.slave_tx_bytes = updated_size;
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ESP_LOGV(TAG, "updated: slave prepared tx buffer is: %d bytes", updated_size);
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return ret;
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}
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previous_size = updated_size;
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}
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}
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esp_err_t essl_spi_get_packet(void *arg, void *out_data, size_t size, uint32_t wait_ms)
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{
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ESP_RETURN_ON_FALSE(arg, ESP_ERR_INVALID_STATE, TAG, "Check ESSL SPI initialization first");
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if (!esp_ptr_dma_capable(out_data) || ((intptr_t)out_data % 4) != 0) {
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return ESP_ERR_INVALID_ARG;
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}
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essl_spi_context_t *ctx = arg;
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esp_err_t ret;
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if (essl_spi_get_rx_data_size(arg) < size) {
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/**
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* For realistic situation, usually there will be a large overhead (Slave will load large amount of data),
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* so here we only update the Slave's TX size when the last-updated size is smaller than what Master requires.
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*/
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ret = essl_spi_update_rx_data_size(arg, wait_ms);
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if (ret != ESP_OK) {
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return ret;
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}
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//Slave still did not load enough size of buffer
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if (essl_spi_get_rx_data_size(arg) < size) {
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ESP_LOGV(TAG, "slave buffer: %d is not enough, %d is required", ctx->master_in.slave_tx_bytes, ctx->master_in.received_bytes + size);
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return ESP_ERR_NOT_FOUND;
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}
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}
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ESP_LOGV(TAG, "get_packet: size to read is: %d", size);
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ret = essl_spi_rddma_seg(ctx->spi, out_data, size, 0);
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if (ret != ESP_OK) {
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return ret;
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}
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ctx->master_in.received_bytes += size;
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return ESP_OK;
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}
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//------------------------------------ TX ----------------------------------//
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esp_err_t essl_spi_write_reg(void *arg, uint8_t addr, uint8_t value, uint8_t *out_value, uint32_t wait_ms)
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{
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essl_spi_context_t *ctx = arg;
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ESP_RETURN_ON_FALSE(arg, ESP_ERR_INVALID_STATE, TAG, "Check ESSL SPI initialization first");
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uint8_t reserved_1_head = ctx->master_out.tx_sync_reg < ctx->master_in.rx_sync_reg ? ctx->master_out.tx_sync_reg : ctx->master_in.rx_sync_reg;
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uint8_t reserved_1_tail = reserved_1_head + 3;
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uint8_t reserved_2_head = ctx->master_out.tx_sync_reg < ctx->master_in.rx_sync_reg ? ctx->master_in.rx_sync_reg : ctx->master_out.tx_sync_reg;
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uint8_t reserved_2_tail = reserved_2_head + 3;
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ESP_RETURN_ON_FALSE(addr < reserved_1_head || (addr > reserved_1_tail && addr < reserved_2_head) || addr > reserved_2_tail, ESP_ERR_INVALID_ARG, TAG, "Invalid address");
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ESP_RETURN_ON_FALSE(out_value == NULL, ESP_ERR_NOT_SUPPORTED, TAG, "This feature is not supported");
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return essl_spi_wrbuf(ctx->spi, &value, addr, sizeof(uint8_t), 0);
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}
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static uint32_t essl_spi_get_tx_buffer_num(void *arg)
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{
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essl_spi_context_t *ctx = arg;
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ESP_LOGV(TAG, "slave rx buffer: %d, master has sent: %d", ctx->master_out.slave_rx_buf_num, ctx->master_out.sent_buf_num);
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return ctx->master_out.slave_rx_buf_num - ctx->master_out.sent_buf_num;
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}
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static esp_err_t essl_spi_update_tx_buffer_num(void *arg, uint32_t wait_ms)
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{
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essl_spi_context_t *ctx = arg;
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uint32_t updated_num;
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uint32_t previous_size;
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esp_err_t ret;
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ret = essl_spi_rdbuf_polling(ctx->spi, (uint8_t *)&previous_size, ctx->master_out.tx_sync_reg, sizeof(uint32_t), 0);
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if (ret != ESP_OK) {
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return ret;
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}
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/**
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* Read until the last 2 reading result are same. Reason:
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* SPI transaction is carried on per 1 Byte. So when Master is reading the shared register, if the
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* register value is changed by Slave at this time, Master may get wrong data.
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*/
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while (1) {
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ret = essl_spi_rdbuf_polling(ctx->spi, (uint8_t *)&updated_num, ctx->master_out.tx_sync_reg, sizeof(uint32_t), 0);
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if (ret != ESP_OK) {
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return ret;
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}
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if (updated_num == previous_size) {
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ctx->master_out.slave_rx_buf_num = updated_num;
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ESP_LOGV(TAG, "updated: slave prepared rx buffer: %d", updated_num);
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return ret;
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}
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previous_size = updated_num;
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}
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}
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esp_err_t essl_spi_send_packet(void *arg, const void *data, size_t size, uint32_t wait_ms)
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{
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ESP_RETURN_ON_FALSE(arg, ESP_ERR_INVALID_STATE, TAG, "Check ESSL SPI initialization first");
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if (!esp_ptr_dma_capable(data)) {
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return ESP_ERR_INVALID_ARG;
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}
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essl_spi_context_t *ctx = arg;
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esp_err_t ret;
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uint32_t buf_num_to_use = (size + ctx->master_out.tx_buffer_size - 1) / ctx->master_out.tx_buffer_size;
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if (essl_spi_get_tx_buffer_num(arg) < buf_num_to_use) {
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/**
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* For realistic situation, usually there will be a large overhead (Slave will load enough number of RX buffers),
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* so here we only update the Slave's RX buffer number when the last-updated number is smaller than what Master requires.
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*/
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ret = essl_spi_update_tx_buffer_num(arg, wait_ms);
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if (ret != ESP_OK) {
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return ret;
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}
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//Slave still did not load a sufficient amount of buffers
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if (essl_spi_get_tx_buffer_num(arg) < buf_num_to_use) {
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ESP_LOGV(TAG, "slave buffer: %d is not enough, %d is required", ctx->master_out.slave_rx_buf_num, ctx->master_out.sent_buf_num + buf_num_to_use);
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return ESP_ERR_NOT_FOUND;
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}
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}
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ESP_LOGV(TAG, "send_packet: size to write is: %d", size);
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ret = essl_spi_wrdma_seg(ctx->spi, data, size, 0);
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if (ret != ESP_OK) {
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return ret;
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}
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ctx->master_out.sent_buf_num += buf_num_to_use;
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return essl_spi_wrdma_done(ctx->spi, 0);
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}
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