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https://github.com/espressif/esp-idf.git
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c2f9392be5
wdt: add support for H2 Closes IDF-6643 and IDF-6678 See merge request espressif/esp-idf!22422
124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include <stddef.h>
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#include "esp_rom_caps.h"
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#include "hal/wdt_types.h"
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#include "hal/wdt_hal.h"
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#include "hal/mwdt_ll.h"
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#if CONFIG_HAL_WDT_USE_ROM_IMPL
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#if ESP_ROM_WDT_INIT_PATCH
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void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescaler, bool enable_intr)
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{
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//Initialize HAL context
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memset(hal, 0, sizeof(wdt_hal_context_t));
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if (wdt_inst == WDT_MWDT0) {
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hal->mwdt_dev = &TIMERG0;
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}
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#if SOC_TIMER_GROUPS >= 2
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else if (wdt_inst == WDT_MWDT1) {
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hal->mwdt_dev = &TIMERG1;
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}
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#endif
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else {
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hal->rwdt_dev = RWDT_DEV_GET();
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}
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hal->inst = wdt_inst;
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if (hal->inst == WDT_RWDT) {
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//Unlock RTC WDT
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rwdt_ll_write_protect_disable(hal->rwdt_dev);
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//Disable RTC WDT, all stages, and all interrupts.
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rwdt_ll_disable(hal->rwdt_dev);
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rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE0);
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rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE1);
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rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE2);
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rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE3);
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#ifdef CONFIG_IDF_TARGET_ESP32
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//Enable or disable level interrupt. Edge interrupt is always disabled.
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rwdt_ll_set_edge_intr(hal->rwdt_dev, false);
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rwdt_ll_set_level_intr(hal->rwdt_dev, enable_intr);
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#else
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//Enable or disable chip reset on timeout, and length of chip reset signal
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rwdt_ll_set_chip_reset_width(hal->rwdt_dev, 0);
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rwdt_ll_set_chip_reset_en(hal->rwdt_dev, false);
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#endif
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rwdt_ll_clear_intr_status(hal->rwdt_dev);
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rwdt_ll_set_intr_enable(hal->rwdt_dev, enable_intr);
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//Set default values
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#if SOC_CPU_CORES_NUM > 1
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rwdt_ll_set_appcpu_reset_en(hal->rwdt_dev, true);
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#endif
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rwdt_ll_set_procpu_reset_en(hal->rwdt_dev, true);
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rwdt_ll_set_pause_in_sleep_en(hal->rwdt_dev, true);
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rwdt_ll_set_cpu_reset_length(hal->rwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
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rwdt_ll_set_sys_reset_length(hal->rwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
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//Lock RTC WDT
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rwdt_ll_write_protect_enable(hal->rwdt_dev);
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} else {
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//Unlock WDT
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mwdt_ll_write_protect_disable(hal->mwdt_dev);
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//Disable WDT and stages.
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mwdt_ll_disable(hal->mwdt_dev);
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mwdt_ll_disable_stage(hal->mwdt_dev, 0);
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mwdt_ll_disable_stage(hal->mwdt_dev, 1);
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mwdt_ll_disable_stage(hal->mwdt_dev, 2);
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mwdt_ll_disable_stage(hal->mwdt_dev, 3);
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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//Enable or disable level interrupt. Edge interrupt is always disabled.
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mwdt_ll_set_edge_intr(hal->mwdt_dev, false);
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mwdt_ll_set_level_intr(hal->mwdt_dev, enable_intr);
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#endif
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mwdt_ll_clear_intr_status(hal->mwdt_dev);
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mwdt_ll_set_intr_enable(hal->mwdt_dev, enable_intr);
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//Set default values
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mwdt_ll_set_cpu_reset_length(hal->mwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
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mwdt_ll_set_sys_reset_length(hal->mwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
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mwdt_ll_set_clock_source(hal->mwdt_dev, MWDT_CLK_SRC_DEFAULT);
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mwdt_ll_enable_clock(hal->mwdt_dev, true);
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//Set tick period
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mwdt_ll_set_prescaler(hal->mwdt_dev, prescaler);
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//Lock WDT
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mwdt_ll_write_protect_enable(hal->mwdt_dev);
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}
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}
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void wdt_hal_deinit(wdt_hal_context_t *hal)
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{
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if (hal->inst == WDT_RWDT) {
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//Unlock WDT
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rwdt_ll_write_protect_disable(hal->rwdt_dev);
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//Disable WDT and clear any interrupts
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rwdt_ll_feed(hal->rwdt_dev);
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rwdt_ll_disable(hal->rwdt_dev);
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rwdt_ll_clear_intr_status(hal->rwdt_dev);
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rwdt_ll_set_intr_enable(hal->rwdt_dev, false);
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//Lock WDT
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rwdt_ll_write_protect_enable(hal->rwdt_dev);
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} else {
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//Unlock WDT
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mwdt_ll_write_protect_disable(hal->mwdt_dev);
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//Disable WDT and clear/disable any interrupts
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mwdt_ll_feed(hal->mwdt_dev);
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mwdt_ll_disable(hal->mwdt_dev);
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mwdt_ll_clear_intr_status(hal->mwdt_dev);
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mwdt_ll_set_intr_enable(hal->mwdt_dev, false);
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mwdt_ll_enable_clock(hal->mwdt_dev, false);
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//Lock WDT
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mwdt_ll_write_protect_enable(hal->mwdt_dev);
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}
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//Deinit HAL context
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hal->mwdt_dev = NULL;
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}
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#endif // ESP_ROM_WDT_INIT_PATCH
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#endif // CONFIG_HAL_WDT_USE_ROM_IMPL
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