Omar Chebib 752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' ... G0: RISC-V targets have now an independent G0 layer See merge request espressif/esp-idf!17926		2022-06-16 11:53:39 +08:00
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esp32	Merge branch 'feature/new_esp_psram_component' into 'master'	2022-06-15 19:16:56 +08:00
esp32c2	Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'	2022-06-16 11:53:39 +08:00
esp32c3	Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'	2022-06-16 11:53:39 +08:00
esp32h2	Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'	2022-06-16 11:53:39 +08:00
esp32s2	Merge branch 'feature/new_esp_psram_component' into 'master'	2022-06-15 19:16:56 +08:00
esp32s3	Merge branch 'feature/new_esp_psram_component' into 'master'	2022-06-15 19:16:56 +08:00
include	esp_psram: new psram component	2022-06-14 15:44:27 +08:00
async_memcpy_impl_gdma.c	global: make periph enable/disable APIs private	2021-11-08 10:37:47 +08:00
esp_memprot_conv.c	System/Security: Memprot API unified (ESP32C3)	2021-12-21 01:50:36 +01:00