mirror of
https://github.com/espressif/esp-idf.git
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301 lines
9.8 KiB
C
301 lines
9.8 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use in application code.
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* See readme.md in soc/include/hal/readme.md
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******************************************************************************/
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// The LL layer for ESP32-S2 PCNT register operations
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#pragma once
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#include "soc/pcnt_periph.h"
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#include "hal/pcnt_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Get PCNT hardware instance with giving pcnt num
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#define PCNT_LL_GET_HW(num) (((num) == 0) ? (&PCNT) : NULL)
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/**
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* @brief Set PCNT counter mode
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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* @param channel PCNT channel number
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* @param pos_mode Counter mode when detecting positive edge
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* @param neg_mode Counter mode when detecting negative edge
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* @param hctrl_mode Counter mode when control signal is high level
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* @param lctrl_mode Counter mode when control signal is low level
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*/
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static inline void pcnt_ll_set_mode(pcnt_dev_t *hw, pcnt_unit_t unit, pcnt_channel_t channel, pcnt_count_mode_t pos_mode, pcnt_count_mode_t neg_mode, pcnt_ctrl_mode_t hctrl_mode, pcnt_ctrl_mode_t lctrl_mode)
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{
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typeof(hw->conf_unit[unit].conf0) conf0_reg = hw->conf_unit[unit].conf0;
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if (channel == 0) {
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conf0_reg.ch0_pos_mode = pos_mode;
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conf0_reg.ch0_neg_mode = neg_mode;
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conf0_reg.ch0_hctrl_mode = hctrl_mode;
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conf0_reg.ch0_lctrl_mode = lctrl_mode;
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} else {
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conf0_reg.ch1_pos_mode = pos_mode;
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conf0_reg.ch1_neg_mode = neg_mode;
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conf0_reg.ch1_hctrl_mode = hctrl_mode;
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conf0_reg.ch1_lctrl_mode = lctrl_mode;
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}
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hw->conf_unit[unit].conf0 = conf0_reg;
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}
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/**
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* @brief Get pulse counter value
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit Pulse Counter unit number
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* @param count Pointer to accept counter value
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*/
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static inline void pcnt_ll_get_counter_value(pcnt_dev_t *hw, pcnt_unit_t unit, int16_t *count)
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{
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*count = (int16_t) hw->cnt_unit[unit].cnt_val;
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}
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/**
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* @brief Pause PCNT counter of PCNT unit
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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*/
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static inline void pcnt_ll_counter_pause(pcnt_dev_t *hw, pcnt_unit_t unit)
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{
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hw->ctrl.val |= BIT(PCNT_CNT_PAUSE_U0_S + (unit * 2));
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}
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/**
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* @brief Resume counting for PCNT counter
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number, select from pcnt_unit_t
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*/
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static inline void pcnt_ll_counter_resume(pcnt_dev_t *hw, pcnt_unit_t unit)
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{
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hw->ctrl.val &= (~(BIT(PCNT_CNT_PAUSE_U0_S + (unit * 2))));
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}
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/**
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* @brief Clear and reset PCNT counter value to zero
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number, select from pcnt_unit_t
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*/
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static inline void pcnt_ll_counter_clear(pcnt_dev_t *hw, pcnt_unit_t unit)
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{
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uint32_t reset_bit = BIT(PCNT_PULSE_CNT_RST_U0_S + (unit * 2));
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hw->ctrl.val |= reset_bit;
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hw->ctrl.val &= ~reset_bit;
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}
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/**
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* @brief Enable PCNT interrupt for PCNT unit
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* @note
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* Each Pulse counter unit has five watch point events that share the same interrupt.
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* Configure events with pcnt_event_enable() and pcnt_event_disable()
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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*/
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static inline void pcnt_ll_intr_enable(pcnt_dev_t *hw, pcnt_unit_t unit)
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{
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hw->int_ena.val |= BIT(PCNT_CNT_THR_EVENT_U0_INT_ENA_S + unit);
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}
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/**
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* @brief Disable PCNT interrupt for PCNT unit
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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*/
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static inline void pcnt_ll_intr_disable(pcnt_dev_t *hw, pcnt_unit_t unit)
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{
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hw->int_ena.val &= (~(BIT(PCNT_CNT_THR_EVENT_U0_INT_ENA_S + unit)));
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}
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/**
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* @brief Get PCNT interrupt status
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param status Pointer to accept value
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*/
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static inline void pcnt_ll_get_intr_status(pcnt_dev_t *hw, uint32_t *status)
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{
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*status = hw->int_st.val;
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}
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/**
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* @brief Clear PCNT interrupt status
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param status value to clear interrupt status
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*/
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static inline void pcnt_ll_clear_intr_status(pcnt_dev_t *hw, uint32_t status)
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{
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hw->int_clr.val = status;
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}
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/**
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* @brief Enable PCNT event of PCNT unit
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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* @param evt_type Watch point event type.
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* All enabled events share the same interrupt (one interrupt per pulse counter unit).
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*/
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static inline void pcnt_ll_event_enable(pcnt_dev_t *hw, pcnt_unit_t unit, pcnt_evt_type_t evt_type)
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{
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if (evt_type == PCNT_EVT_L_LIM) {
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hw->conf_unit[unit].conf0.thr_l_lim_en = 1;
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} else if (evt_type == PCNT_EVT_H_LIM) {
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hw->conf_unit[unit].conf0.thr_h_lim_en = 1;
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} else if (evt_type == PCNT_EVT_THRES_0) {
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hw->conf_unit[unit].conf0.thr_thres0_en = 1;
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} else if (evt_type == PCNT_EVT_THRES_1) {
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hw->conf_unit[unit].conf0.thr_thres1_en = 1;
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} else if (evt_type == PCNT_EVT_ZERO) {
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hw->conf_unit[unit].conf0.thr_zero_en = 1;
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}
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}
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/**
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* @brief Disable PCNT event of PCNT unit
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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* @param evt_type Watch point event type.
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* All enabled events share the same interrupt (one interrupt per pulse counter unit).
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*/
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static inline void pcnt_ll_event_disable(pcnt_dev_t *hw, pcnt_unit_t unit, pcnt_evt_type_t evt_type)
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{
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if (evt_type == PCNT_EVT_L_LIM) {
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hw->conf_unit[unit].conf0.thr_l_lim_en = 0;
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} else if (evt_type == PCNT_EVT_H_LIM) {
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hw->conf_unit[unit].conf0.thr_h_lim_en = 0;
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} else if (evt_type == PCNT_EVT_THRES_0) {
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hw->conf_unit[unit].conf0.thr_thres0_en = 0;
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} else if (evt_type == PCNT_EVT_THRES_1) {
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hw->conf_unit[unit].conf0.thr_thres1_en = 0;
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} else if (evt_type == PCNT_EVT_ZERO) {
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hw->conf_unit[unit].conf0.thr_zero_en = 0;
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}
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}
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/**
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* @brief Set PCNT event value of PCNT unit
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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* @param evt_type Watch point event type.
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* All enabled events share the same interrupt (one interrupt per pulse counter unit).
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*
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* @param value Counter value for PCNT event
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*/
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static inline void pcnt_ll_set_event_value(pcnt_dev_t *hw, pcnt_unit_t unit, pcnt_evt_type_t evt_type, int16_t value)
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{
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if (evt_type == PCNT_EVT_L_LIM) {
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hw->conf_unit[unit].conf2.cnt_l_lim = value;
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} else if (evt_type == PCNT_EVT_H_LIM) {
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hw->conf_unit[unit].conf2.cnt_h_lim = value;
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} else if (evt_type == PCNT_EVT_THRES_0) {
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hw->conf_unit[unit].conf1.cnt_thres0 = value;
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} else if (evt_type == PCNT_EVT_THRES_1) {
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hw->conf_unit[unit].conf1.cnt_thres1 = value;
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}
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}
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/**
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* @brief Get PCNT event value of PCNT unit
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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* @param evt_type Watch point event type.
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* All enabled events share the same interrupt (one interrupt per pulse counter unit).
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* @param value Pointer to accept counter value for PCNT event
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*/
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static inline void pcnt_ll_get_event_value(pcnt_dev_t *hw, pcnt_unit_t unit, pcnt_evt_type_t evt_type, int16_t *value)
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{
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if (evt_type == PCNT_EVT_L_LIM) {
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*value = (int16_t) hw->conf_unit[unit].conf2.cnt_l_lim;
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} else if (evt_type == PCNT_EVT_H_LIM) {
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*value = (int16_t) hw->conf_unit[unit].conf2.cnt_h_lim;
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} else if (evt_type == PCNT_EVT_THRES_0) {
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*value = (int16_t) hw->conf_unit[unit].conf1.cnt_thres0;
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} else if (evt_type == PCNT_EVT_THRES_1) {
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*value = (int16_t) hw->conf_unit[unit].conf1.cnt_thres1;
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} else {
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*value = 0;
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}
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}
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/**
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* @brief Set PCNT filter value
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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* @param filter_val PCNT signal filter value, counter in APB_CLK cycles.
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* Any pulses lasting shorter than this will be ignored when the filter is enabled.
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* @note
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* filter_val is a 10-bit value, so the maximum filter_val should be limited to 1023.
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*/
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static inline void pcnt_ll_set_filter_value(pcnt_dev_t *hw, pcnt_unit_t unit, uint16_t filter_val)
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{
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hw->conf_unit[unit].conf0.filter_thres = filter_val;
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}
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/**
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* @brief Get PCNT filter value
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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* @param filter_val Pointer to accept PCNT filter value.
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*/
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static inline void pcnt_ll_get_filter_value(pcnt_dev_t *hw, pcnt_unit_t unit, uint16_t *filter_val)
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{
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*filter_val = hw->conf_unit[unit].conf0.filter_thres;
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}
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/**
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* @brief Enable PCNT input filter
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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*/
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static inline void pcnt_ll_filter_enable(pcnt_dev_t *hw, pcnt_unit_t unit)
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{
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hw->conf_unit[unit].conf0.filter_en = 1;
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}
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/**
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* @brief Disable PCNT input filter
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*
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* @param hw Peripheral PCNT hardware instance address.
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* @param unit PCNT unit number
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*/
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static inline void pcnt_ll_filter_disable(pcnt_dev_t *hw, pcnt_unit_t unit)
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{
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hw->conf_unit[unit].conf0.filter_en = 0;
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}
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#ifdef __cplusplus
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}
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#endif |